After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

Implemented by making lib/CompilerDriver a shared library that holds all the
global static data (CommandLine options, plugin registry) that we unfortunately
have to live with.

llvm-svn: 74417

llvm-svn: 74416

llvm-svn: 74415

llvm-svn: 74402

llvm-svn: 74401

llvm-svn: 74400

doesn't have an IV-based operand. This fixes PR4471.

llvm-svn: 74399

LoopInfo will handle removing it from the Loop, as well as updating
its own tables.

llvm-svn: 74398

when one of them can be converted to a trivial icmp and conditional
branch.

This addresses what is essentially a phase ordering problem.
SimplifyCFG knows how to do this transformation, but it doesn't do so
if the primary block has any instructions in it other than an icmp and
a branch. In the given testcase, the block contains other instructions,
however they are loop-invariant and can be hoisted. SimplifyCFG doesn't
have LoopInfo though, so it can't hoist them. And, it's important that
the blocks be merged before LoopRotation, as it doesn't support
multiple-exit loops.

llvm-svn: 74396

llvm-svn: 74395

llvm-svn: 74394

of a team of individual allocations and a team of std::maps.

llvm-svn: 74393

llvm-svn: 74391

llvm-svn: 74385

llvm-svn: 74384

llvm-svn: 74382

target-specific operand printing functionality.  Yay.

llvm-svn: 74379

llvm-svn: 74378

llvm-svn: 74377

inserted to replace that value must dominate all of of the basic
blocks associated with the uses of the value in the PHI, not just
one of them.

llvm-svn: 74376

llvm-svn: 74375

a base register.  We just ignore it for now.

llvm-svn: 74374

globals.  This implements remat-constant.ll even without aggressive-remat.

llvm-svn: 74373

implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not.  Instead, those decisions are made by isel lowering
and propagated through to the asm printer.  To achieve this, we:

1. Represent RIP relative addresses by setting the base of the X86 addr
   mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
   X86ISD::WrapperRIP.  When it is unsafe to use RIP, it lowers to
   X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
   a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
   passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
   when to emit (%rip), they just print the symbol.

I think this is a big improvement over the previous situation.  It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier.  This is a short term hack, there is
a much better, but more involved, solution.  2. I had to xfail an 
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction.  This specific test is easy to fix without
-aggressive-remat, which I intend to do next.

llvm-svn: 74372

by Evan.

llvm-svn: 74370

llvm-svn: 74368

llvm-svn: 74366

llvm-svn: 74364

llvm-svn: 74357

When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.

llvm-svn: 74355

This helps it avoid reusing an instruction that doesn't dominate all
of the users, in cases where the original instruction was inserted
before all of the users were known.  This may result in redundant
expansions of sub-expressions that depend on loop-unpredictable values
in some cases, however this isn't very common, and it primarily impacts
IndVarSimplify, so GVN can be expected to clean these up.

This eliminates the need for IndVarSimplify's FixUsesBeforeDefs,
which fixes several bugs.

llvm-svn: 74352

llvm-svn: 74351

Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems.

llvm-svn: 74350

nesting order of nested AddRec expressions to skip the transformation
if it would introduce an AddRec with operands not loop-invariant
with respect to its loop.

llvm-svn: 74343

are loop invariant, not just the start operand.

llvm-svn: 74338

Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.

llvm-svn: 74336

llvm-svn: 74334

llvm-svn: 74332

llvm-svn: 74330