Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.

llvm-svn: 152997

This results in things such as

	vmovaps	-96(%rbx), %xmm1
	vinsertf128	$1, %xmm1, %ymm0, %ymm0

to be combined to
         
	vinsertf128	$1, -96(%rbx), %ymm0, %ymm0

rdar://10643481

llvm-svn: 152762

instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().

llvm-svn: 152654

registers not both being 64-bit or both being 32-bit registers.

llvm-svn: 152580

llvm-svn: 152538

llvm-svn: 152507

llvm-svn: 152495

Patch by Kay Tiong Khoo!

llvm-svn: 152487

llvm-svn: 152443

prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.

llvm-svn: 152414

llvm-svn: 152391

Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078

llvm-svn: 152366

llvm-svn: 152136

Used to allow context sensitive printing of super-register or sub-register
references.

llvm-svn: 152043

Specifically, remove the magic number when checking to see if the copy has a 
glue operand and simplify the checking logic.

rdar://10930395

llvm-svn: 152041

llvm-svn: 152014

llvm-svn: 152001

llvm-svn: 151996

Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o

llvm-svn: 151995

In this instance we are generating the tail-call during legalizeDAG.  The 2nd
floor call can't be a tail call because it clobbers %xmm1, which is defined by
the first floor call.  The first floor call can't be a tail-call because it's
not in the tail position.  The only reasonable way I could think to fix this
in a target-independent manner was to check for glue logic on the copy reg.

rdar://10930395

llvm-svn: 151877

llvm-svn: 151849

So with darwin's otool(1) an x86_64 hello world .o file will print:
leaq	L_.str(%rip), %rax ## literal pool for: Hello world

llvm-svn: 151769

Patch by Tyler Nowicki!

llvm-svn: 151743

llvm-svn: 151687

llvm-svn: 151645

Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.

llvm-svn: 151630

the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623

This patch adds instruction latencies for the SSE instructions
to the instruction scheduler for the Intel Atom.

llvm-svn: 151590

rdar://10921670
PR11935

llvm-svn: 151543

llvm-svn: 151510

Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 lowering for i386-*-win32 targets. Patch by Joe Groff.

[Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems:
Clang raised a warning, and X86 LowerOperation would assert out for
fptoui f64 to i32 because it improperly lowered to an illegal
BUILD_PAIR. Here's a patch that addresses these issues. Let me know if
any other changes are necessary. Thanks.

llvm-svn: 151432

used by the Win32 _ftol2 runtime function. Patch by Joe Groff!

llvm-svn: 151382

Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics

llvm-svn: 151342

rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267

Patch by Joe Groff!

llvm-svn: 151183

llvm-svn: 151169

Declare register classes as const. Fix a couple pointers to register classes that weren't already const.

llvm-svn: 151138

Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.

llvm-svn: 151134

llvm-svn: 151123

llvm-svn: 150918