llvm-svn: 78478

 - Part of optimal static profiling patch sequence by Andreas Neustifter.

 - Store edge, block, and function information separately for each functions
   (instead of in one giant map).

 - Return frequencies as double instead of int, and use a sentinel value for
   missing information.

llvm-svn: 78477

Handle large integers, x86_fp80, ConstantAggregateZero, and two more ConstantExpr:
GetElementPtr and IntToPtr
Set SHF_MERGE bit for mergeable strings
Avoid zero initialized strings to be classified as a bss symbol
Don't allow common symbols to be classified as STB_WEAK
Add a constant to be used as a global value offset in data relocations 

llvm-svn: 78476

llvm-svn: 78475

llvm-svn: 78474

the new havior is better so...

llvm-svn: 78473

Also don't dereference old pointers after they have been deleted causing
random crashes when enabling the machine code verifier.

Ahem...

I have not included a test case for the crash. It hapened when enabling the
verifier on CodeGen/X86/2009-08-06-branchfolder-crash.ll.

The crash depends on an MBB being allocated at the same address as a
previously deleted MBB. I don't think that can be reproduced reliably.

llvm-svn: 78472

llvm-svn: 78471

Did anyone tests v4f32 ever?

llvm-svn: 78470

llvm-svn: 78469

llvm-svn: 78468

* Cleaner handling of <undef>.
* <def> takes precedence over <def,dead>.
* Implement the OK-to-redefine-a-register-that-was-
  live-in-but-has-not-been-used-before rule.

llvm-svn: 78467

Now there is no special treatment of instructions that redefine part of a
super-register. Instead, the super-register is marked with <imp-use,kill> and
<imp-def>. For instance, from LowerSubregs on ARM:

subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def>

subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6
subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def>
llvm-svn: 78466

Verify that early clobber registers and their aliases are not used.

All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.

The included test case is from PR4686. It has behaviour that was dependent on the order of operands.

llvm-svn: 78465

llvm-svn: 78464

llvm-svn: 78463

llvm-svn: 78462

 - This doesn't actually improve the algorithm (its still linear), but the
   generated (match) code is now fairly compact and table driven. Still need a
   generic string matcher.

 - The table still needs to be compressed, this is quite simple to do and should
   shrink it to under 16k.

 - This also simplifies and restructures the code to make the match classes more
   explicit, in anticipation of resolving ambiguities.

llvm-svn: 78461

so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460

directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459

so that terminal states are as simple as possible.
 - If we were willing to assume that the order that operands get inserted in the
   MCInst is fixed we could actually dispose with this altogether, although it
   might be nice to have the flexibility to change it later.

llvm-svn: 78458

llvm-svn: 78457

llvm-svn: 78456

llvm-svn: 78455

llvm-svn: 78454

llvm-svn: 78453

llvm-svn: 78452

llvm-svn: 78451

to allow sharing of nodes. Simplifies some aspects of template
instantiation, and fixes both PR3444 and <rdar://problem/6757457>.

llvm-svn: 78450

error condition get trapped with an assert.

llvm-svn: 78449

llvm-svn: 78448

llvm-svn: 78447

llvm-svn: 78446

non-trivial copy constructors.

llvm-svn: 78445

llvm-svn: 78444

llvm-svn: 78443

llvm-svn: 78441

is more tolerant of whitespace differences.

llvm-svn: 78439

as vector shuffles did not work out well.  Shuffles that produce double-wide
vectors accurately represent the operation but make it hard to do anything
with the results.  I considered splitting them up into 2 shuffles, one to
write each register separately, but there doesn't seem to be a good way to
reunite them for codegen.

llvm-svn: 78437

copying non-virtual base classes which have non-trivial
constructor. Work in progress.

llvm-svn: 78436