llvm-svn: 124077

clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

llvm-svn: 124073

llvm-svn: 124071

that have PHI or select uses of their element pointers.  This can often happen
when instcombine sinks two loads into a successor, inserting a phi or select.

With this patch, we can scalarize the alloca, but the pinned elements are not
yet promoted.  This is still a win for large aggregates where only one element
is used.  This fixes rdar://8904039 and part of rdar://7339113 (poor codegen
on stringswitch).

llvm-svn: 124070

on test-suite + SPEC2000 & SPEC2006.

llvm-svn: 124068

No functionality change.

llvm-svn: 124067

handle the "Transformation preventing inst" printing, 
so that -scalarrepl -debug will always print the rejected
instruction.  No functionality change.

llvm-svn: 124066

llvm-svn: 124065

X86 backend has been fixed.

llvm-svn: 124064

llvm-svn: 124062

computation, the Ancestor field is always set to the Parent, so we can remove
the explicit link entirely and merge the Parent and Ancestor fields. Instead of
checking for whether an ancestor exists for a node or not, we simply check
whether the node has already been processed. This is simpler if Compress is
inlined into Eval, so I did that as well.

This is about a 3% speedup running -domtree on test-suite + SPEC2000 & SPEC2006,
but it also opens up some opportunities for further improvement.

llvm-svn: 124061

Add support for SHT_X86_64_UNWIND.

llvm-svn: 124059

llvm-svn: 124058

llvm-svn: 124057

llvm-svn: 124056

llvm-svn: 124055

llvm-svn: 124054

of the link-eval data structure from dominator computation.

llvm-svn: 124053

"make check" alone.

llvm-svn: 124046

that we can change from indirect to direct.

llvm-svn: 124045

target function.

Fixes part of rdar://8546196

llvm-svn: 124044

Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI.

llvm-svn: 124030

llvm-svn: 124028

llvm-svn: 124027

llvm-svn: 124026

llvm-svn: 124019

how they should be checked.

llvm-svn: 123999

 Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.

llvm-svn: 123997

A == B, and A > B, does not mean we can fold it to true.  We still need to
check for A ? B (A unordered B).

llvm-svn: 123993

1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991

Clang was not parsing target triples involving EABI and was generating wrong IR (wrong PCS) and passing the wrong information down llc via the target-triple printed in IR. I've fixed this by adding the parsing of EABI into LLVM's Triple class and using it to choose the correct PCS in Clang's Tools. A Clang patch is on its way to use this infrastructure.

llvm-svn: 123990

Patch by arrowdodger!

llvm-svn: 123976

qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975

llvm-svn: 123974

instructions.

llvm-svn: 123973

This reverts commit 281f3901b7b0869929caf8946c1ad1228bc38922.

llvm-svn: 123972

DAG. Disable using "-disable-sched-cycles".

For ARM, this enables a framework for modeling the cpu pipeline and
counting stalls. It also activates several heuristics to drive
scheduling based on the model. Scheduling is inherently imprecise at
this stage, and until spilling is improved it may defeat attempts to
schedule. However, this framework provides greater control over
tuning codegen.

Although the flag is not target-specific, it should have very little
affect on the default scheduler used by x86. The only two changes that
affect x86 are:
- scheduling a high-latency operation bumps the current cycle so independent
  operations can have their latency covered. i.e. two independent 4
  cycle operations can produce results in 4 cycles, not 8 cycles.
- Two operations with equal register pressure impact and no
  latency-based stalls on their uses will be prioritized by depth before height
  (height is irrelevant if no stalls occur in the schedule below this point).

llvm-svn: 123971

flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.

llvm-svn: 123969

llvm-svn: 123968

llvm-svn: 123965