- Jan 28, 2012
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James Molloy authored
Fixes PR11877 llvm-svn: 149180
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- Jan 27, 2012
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Devang Patel authored
llvm-svn: 149142
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Craig Topper authored
Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition. llvm-svn: 149122
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Jim Grosbach authored
llvm-svn: 149106
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Jim Grosbach authored
llvm-svn: 149102
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Jim Grosbach authored
Provide source line number information. llvm-svn: 149101
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Jim Grosbach authored
Adjust an example MachObjectWriter diagnostic to use the information to issue a better message. Before: LLVM ERROR: unknown ARM fixup kind! After: x.s:6:5: error: unsupported relocation on symbol beq bar ^ rdar://9800182 llvm-svn: 149093
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- Jan 26, 2012
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Jakob Stoklund Olesen authored
The Win64 calling convention has xmm6-15 as callee-saved while still clobbering all ymm registers. Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the ymm registers, and mark that as call-clobbered. This allows live xmm registers across calls. This hack wouldn't be necessary with RegisterMask operands representing the call clobbers, but they are not quite operational yet. llvm-svn: 149088
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Jim Grosbach authored
llvm-svn: 149062
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James Molloy authored
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
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Victor Umansky authored
. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode. . Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode. . Consequently, the conversion produces incorrect numbers. The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows. The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). llvm-svn: 149056
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Craig Topper authored
llvm-svn: 149054
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Craig Topper authored
llvm-svn: 149053
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Craig Topper authored
llvm-svn: 149052
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- Jan 25, 2012
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Anton Korobeynikov authored
and let linker handle the rest. This finally fixes PR5329 llvm-svn: 148990
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Jim Grosbach authored
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 llvm-svn: 148969
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Chris Lattner authored
Thanks to Eli for noticing. llvm-svn: 148947
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Craig Topper authored
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. llvm-svn: 148933
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Chris Lattner authored
llvm-svn: 148929
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Craig Topper authored
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. llvm-svn: 148927
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Craig Topper authored
llvm-svn: 148922
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Akira Hatanaka authored
llvm-svn: 148918
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Akira Hatanaka authored
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. llvm-svn: 148917
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Akira Hatanaka authored
expand offsets that do not fit in the 16-bit immediate field of load and store instructions. Also change the types of variables so that they are sufficiently large to handle 64-bit pointers. llvm-svn: 148916
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Craig Topper authored
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. llvm-svn: 148914
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NAKAMURA Takumi authored
inttypes.h is not supplied in msvc. llvm-svn: 148912
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NAKAMURA Takumi authored
llvm-svn: 148909
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Akira Hatanaka authored
Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. llvm-svn: 148908
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Akira Hatanaka authored
load an immediate. llvm-svn: 148900
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Jim Grosbach authored
llvm-svn: 148884
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Jim Grosbach authored
llvm-svn: 148883
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Jim Grosbach authored
llvm-svn: 148882
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Akira Hatanaka authored
which is what N32/64 does. llvm-svn: 148875
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- Jan 24, 2012
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Akira Hatanaka authored
llvm-svn: 148871
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Akira Hatanaka authored
llvm-svn: 148869
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Devang Patel authored
llvm-svn: 148864
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Akira Hatanaka authored
llvm-svn: 148862
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Jim Grosbach authored
llvm-svn: 148836
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Owen Anderson authored
Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. llvm-svn: 148833
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Jim Grosbach authored
llvm-svn: 148832
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