provide a 'fixit' to change 'readonly' to 'readwrite'. // rdar://11448209

llvm-svn: 157193

data.

llvm-svn: 157192

Patch by Jose Fonseca.

llvm-svn: 157191

<rdar://problem/11355592> Fixing a bug where we would incorrectly try and determine a dynamic type for a variable of a pointer type that is not a valid generic type for dynamic pointers.

llvm-svn: 157190

llvm-svn: 157188

llvm-svn: 157187

attributes.

llvm-svn: 157186

llvm-svn: 157184

PR1255 (case ranges: work with ConstantRangesSet instead of ConstantInt) related changes for Execution and Verifier.

llvm-svn: 157183

In theory they should be wide enough even when the enum type is signed, but it
looks like MSVC9 still has problems with it.

llvm-svn: 157182

llvm-svn: 157181

llvm-svn: 157178

tests like to try to malloc((size_t)-1)

llvm-svn: 157176

Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces.

llvm-svn: 157175

This helps compile time when the greedy register allocator splits live
ranges in giant functions. Without the bias, we would try to grow
regions through the giant edge bundles, usually to find out that the
region became too big and expensive.

If a live range has many uses in blocks near the giant bundle, the small
negative bias doesn't make a big difference, and we still consider
regions including the giant edge bundle.

Giant edge bundles are usually connected to landing pads or indirect
branches.

llvm-svn: 157174

llvm-svn: 157173

header searches with CUDA.

llvm-svn: 157172

to deal with NVIDIA's headers.  We'll need to think of another way
to handle multiple host/device definitions within the same TU.

llvm-svn: 157171

llvm-svn: 157170

With physreg joining out of the way, it is easy to recognize the
instructions that need their kill flags cleared while testing for
interference.

This allows us to skip the final scan of all instructions for an 11%
speedup of the coalescer pass.

llvm-svn: 157169

Because in CUDA types do not have associated address spaces,
globals are declared in their "native" address space, and accessed
by bitcasting the pointer to address space 0.  This relies on address
space 0 being a unified address space.

llvm-svn: 157167

llvm-svn: 157166

It can sometimes be used in addressing modes that don't support %ESP.

llvm-svn: 157165

It can be necessary to restrict to a sub-class before accessing
sub-registers.

llvm-svn: 157164

When rewriting operands, make sure the new registers have a compatible
register class.

llvm-svn: 157163

may be RAUW'd by the recursive call to LegalizeOps; instead, retrieve
the other operands when calling UpdateNodeOperands.  Fixes PR12889.

llvm-svn: 157162

There should be no difference in the resulting binary, given a sufficiently
smart compiler. However we already had compiler timeouts on the generated
code in Intrinsics.gen, this hopefully makes the lives of slow buildbots a
little easier.

llvm-svn: 157161

Found by valgrind.

llvm-svn: 157160

This seems to fix the remaining compile-time failures on PPC64 when
compiling with -enable-ppc-preinc.

llvm-svn: 157159

llvm-svn: 157158

llvm-svn: 157157

llvm-svn: 157155

llvm-svn: 157154

llvm-svn: 157152

They need to go on the PICLDR as the verifier points out.

llvm-svn: 157151

Not all GR64 registers have sub_8bit sub-registers.

llvm-svn: 157150

X86 has 2-addr instructions with different constraints on the tied def
and use operands. One is GR32, one is GR32_NOSP.

llvm-svn: 157149

llvm-svn: 157148

This function adds copies to be erased to DupCopies, avoid also adding
them to DeadCopies.

llvm-svn: 157147

Avoid looking at the operands of a potentially erased instruction.

llvm-svn: 157146