llvm-svn: 117057

half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.

llvm-svn: 117056

llvm-svn: 117055

mostly based on the ARM AsmParser at this time and is not particularly
functional.

Changed the MBlaze data layout from:
    "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
    "E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.

Cleaned up the MBlaze source code:
    1. The floating point register class has been removed. The
       MicroBlaze does not have floating point registers. Floating
       point values are simply stored in integer registers.
    2. Renaming the CPURegs register class to GPR to reflect the
       standard naming.
    3. Removing a lot of stale code from AsmPrinter after
       the conversion to InstPrinter.
    4. Simplified sign extended loads by marking them as
       expanded in ISelLowering.

llvm-svn: 117054

llvm-svn: 117053

the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051

llvm-svn: 117050

llvm-svn: 117048

llvm-svn: 117047

Parent - union(Y, ...). Doh.

llvm-svn: 117042

unconditional branch.

llvm-svn: 117041

llvm-svn: 117040

llvm-svn: 117039

from losing the variant when producing a relocation on an alias.

llvm-svn: 117037

sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031

llvm-svn: 117025

in assigning it to a variable (gcc-4.6 warning).

llvm-svn: 117024

it looks like maybe it was supposed to be used in the
test...), so zap it (gcc-4.6 warning).

llvm-svn: 117023

(gcc-4.6 warning).

llvm-svn: 117022

(gcc-4.6 warns about these).

llvm-svn: 117021

llvm-svn: 117020

Better late than never, right?

llvm-svn: 117009

deregisters registered by it FDE structures allowing consecutive
JIT runs to succeed.  Patch by Yuri.  Fixes PR8285.

llvm-svn: 117004

llvm-svn: 117002

llvm-svn: 116998

CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.

llvm-svn: 116997

llvm-svn: 116993

llvm-svn: 116992

compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.

llvm-svn: 116991

llvm-svn: 116987

    1. A delay slot filler that searches for valid instructions
       to fill the delay slot with. Previously NOPs would always
       be inserted into delay slots.
    2. Support for MC based instruction printer added.
    3. Support for MC based machine code generation and ELF
       file generation. ELF file generation does not yet
       completely work as much of the ELF support infrastructure
       is still x86/x86-64 specific.
    4. General clean up of the MBlaze backend code. Much of the
       tablegen code has been cleanup and simplified.

Bug Fixes:
    1. Removed duplicate periods from subtarget feature descriptions.
    2. Many of the instructions had bad machine code information
       in the tablegen files. Much of this has been fixed.

llvm-svn: 116986

support future ELF file generation by the MBlaze backend.

llvm-svn: 116985

llvm-svn: 116984

llvm-svn: 116983

llvm-svn: 116981

This should be the minimum set of functions that could possibly need it.

llvm-svn: 116978

llvm-svn: 116977

llvm-svn: 116972

extension register.

llvm-svn: 116970

llvm-svn: 116962