llvm-svn: 107122

llvm-svn: 107121

llvm-svn: 107114

the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107

of the Subtarget.

llvm-svn: 107086

llvm-svn: 107073

llvm-svn: 107070

llvm-svn: 107068

llvm-svn: 106988

llvm-svn: 106940

llvm-svn: 106938

llvm-svn: 106935

llvm-svn: 106927

"N..." instead of "NEON..." for consistency with the other NEON format names.

llvm-svn: 106921

Renumber MiscFrm to 25.

llvm-svn: 106916

introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.

llvm-svn: 106908

llvm-svn: 106901

emitNEON2RegInstruction's handling of 2-address operands.

llvm-svn: 106900

for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.

llvm-svn: 106893

llvm-svn: 106891

llvm-svn: 106881

with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.

Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.

llvm-svn: 106871

Radar 8128745.

llvm-svn: 106820

llvm-svn: 106819

llvm-svn: 106775

llvm-svn: 106770

form so they can be narrowed to 16-bit instructions.

llvm-svn: 106762

void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.

llvm-svn: 106693

branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.

llvm-svn: 106662

MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

llvm-svn: 106631

Radar 8031193.

llvm-svn: 106582

llvm-svn: 106542

llvm-svn: 106517

Radar 8104310.

llvm-svn: 106484

being moved around away from the jump table it references. rdar://8104340

llvm-svn: 106483

Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.

llvm-svn: 106481

handling, plus correct R9 handling in that mode.

llvm-svn: 106434

llvm-svn: 106430

llvm-svn: 106399

llvm-svn: 106382