llvm-svn: 113526

Next step is to recalculate the threshold values given this new heuristic.

llvm-svn: 113525

llvm-svn: 113523

llvm-svn: 113522

llvm-svn: 113521

instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513

- This code is gross, but does the job for now.

llvm-svn: 113509

llvm-svn: 113508

llvm-svn: 113501

Refactor code-size reduction estimation methods out of InlineCostAnalyzer and into CodeMetrics.  They
don't use any InlineCostAnalyzer state, and are useful for other clients who don't necessarily want to use
all of InlineCostAnalyzer's logic, some of which is fairly inlining-specific.

No intended functionality change.

llvm-svn: 113499

large object file (> 1GB).

llvm-svn: 113494

llvm-svn: 113486

llvm-svn: 113478

the VST pseudos.  The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.

llvm-svn: 113473

llvm-svn: 113463

uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX.  No (intended) functional change.

llvm-svn: 113462

llvm-svn: 113461

llvm-svn: 113459

operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

llvm-svn: 113456

llvm-svn: 113455

for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.

llvm-svn: 113453

For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.

llvm-svn: 113452

llvm-svn: 113442

llvm-svn: 113440

Relax the "don't unroll loops containing calls" rule.  Instead, when a loop contains a call, lower the
unrolling threshold to the optimize-for-size threshold.  Basically, for loops containing calls, unrolling
can still be profitable as long as the loop is REALLY small.

llvm-svn: 113439

llvm-svn: 113436

llvm-svn: 113435

llvm-svn: 113427

llvm-svn: 113426

Generalize instcombine's support for combining multiple bit checks into a single test.  Patch by Dirk Steinke!

llvm-svn: 113423

llvm-svn: 113422

llvm-svn: 113420

llvm-svn: 113417

llvm-svn: 113409

llvm-svn: 113406

Re-running some nightly testers w/ it enabled to verify.

llvm-svn: 113399

pointer was intended. rdar://8401980

llvm-svn: 113394

Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.

llvm-svn: 113388

llvm-svn: 113387

llvm-svn: 113386