Turn this:
movswl  %ax, %eax
movl    %eax, -36(%ebp)
xorl    %edi, -36(%ebp)
into
movswl  %ax, %eax
xorl    %edi, %eax
movl    %eax, -36(%ebp)
by unfolding the load / store xorl into an xorl and a store when we know the
value in the spill slot is available in a register. This doesn't change the
number of instructions but reduce the number of times memory is accessed.

Also unfold some load folding instructions and reuse the value when similar
situation presents itself.

llvm-svn: 42947

register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.

llvm-svn: 42946

llvm-svn: 42945

llvm-svn: 42935

for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934

Do not filter memmove.

llvm-svn: 42930

longer be created for fastcc functions.

llvm-svn: 42925

llvm-svn: 42924

llvm-svn: 42922

llvm-svn: 42920

llvm-svn: 42919

llvm-svn: 42916

llvm-svn: 42913

from user input strings.

Such conversions are more intricate and subtle than they may appear;
it is unlikely I have got it completely right first time.  I would
appreciate being informed of any bugs and incorrect roundings you
might discover.

llvm-svn: 42912

llvm-svn: 42911

If we're trying to be arbitrary precision, unsigned char clearly won't cut it.  Needed for dec->bin conversions.

llvm-svn: 42910

llvm-svn: 42909

function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908

llvm-svn: 42907

is a scalar integer.

llvm-svn: 42906

llvm-svn: 42905

llvm-svn: 42904

llvm-svn: 42903

(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.

llvm-svn: 42899

llvm-svn: 42898

llvm-svn: 42895

llvm-svn: 42894

llvm-svn: 42892

Fix DecomposeSimpleLinearExpr to handle simple constants better.
Don't nuke gep(bitcast(allocation)) if the bitcast(allocation) will
fold the allocation.  This fixes PR1728 and Instcombine/malloc3.ll

llvm-svn: 42891

llvm-svn: 42888

may be overloaded with vector types. And add a testcase for codegen for
these.

llvm-svn: 42885

Factor out the code that expands the "nasty scalar code" for unrolling
vectors into a separate routine, teach it how to handle mixed
vector/scalar operands, as seen in powi, and use it for several operators,
including sin, cos, powi, and pow.

Add support in SplitVectorOp for fpow, fpowi and for several unary
operators.

llvm-svn: 42884

Make ppc long double constants print.

llvm-svn: 42882

llvm-svn: 42881

llvm-svn: 42880

llvm-svn: 42879

llvm-svn: 42874

return NULL.

llvm-svn: 42871

enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870

No compile-time support for constant operations yet,
just format transformations.  Make readers and
writers work.  Split constants into 2 doubles in
Legalize.

llvm-svn: 42865