llvm-svn: 47500

Really really bad local register allocator bug. On X86, it was never using ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when
it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.

llvm-svn: 47499

llvm-svn: 47496

llvm-svn: 47492

the way through.  It is now used for codegen.

llvm-svn: 47484

the definition of the operand also reaches its uses.

llvm-svn: 47475

llvm-svn: 47468

that a value is >= 32, check that all of the high bits are zero, not
just one or more.

llvm-svn: 47467

early clobbers if the clobber list contains a *register* not some thing
like {memory}, {dirflag} etc.

llvm-svn: 47457

any, we force sdisel to do all regalloc for an asm.  This
leads to gross but correct codegen.

This fixes the rest of PR2078.

llvm-svn: 47454

llvm-svn: 47453

llvm-svn: 47452

llvm-svn: 47448

llvm-svn: 47435

Atomic op support.  If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet

llvm-svn: 47430

Eli Friedman.  This implements CodeGen/Generic/2008-02-20-MatchingMem.ll.

llvm-svn: 47428

inline asms.

Fix PR2078 by marking aliases of registers used when a register is 
marked used.  This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.

llvm-svn: 47426

llvm-svn: 47416

No need to go up more levels. A def of a register also sets its sub-registers
(so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are
not previously defined).

llvm-svn: 47399

llvm-svn: 47395

llvm-svn: 47389

llvm-svn: 47388

and splitting extract_subvector.  This fixes nine
"make check" testcases, for example
2008-02-04-ExtractSubvector.ll and (partially)
CodeGen/Generic/vector.ll.

llvm-svn: 47384

llvm-svn: 47383

llvm-svn: 47382

llvm-svn: 47381

llvm-svn: 47380

llvm-svn: 47375

llvm-svn: 47368

llvm-svn: 47367

Added two "FIXMEs" for code that looks dubious to me (but I could be
wrong).

llvm-svn: 47366

changes. (Sorry for any formatting changes that creeped in.)

llvm-svn: 47362

AddNodeIDNode does profiling for a ConstantSDNode, but so does 
SelectionDAG::getConstant.  This profiling should be moved to a common
static function in ConstantSDNode.

llvm-svn: 47359

 - Constified some MachineOperand values.
 - Added/Modified some comments.

llvm-svn: 47358

llvm-svn: 47348

PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in order to save a single instruction since a branch will be inserted for each BB.

llvm-svn: 47301

- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.

llvm-svn: 47290

- For now, conservatively ignore copy MI whose source is a physical register. Commuting its def MI can cause a physical register live interval to be live through a loop (since we know it's live coming into the def MI).

llvm-svn: 47281

New helper function getMBBFromIndex() that given an index in any instruction of an MBB returns a pointer the MBB. Reviewed by Evan.

llvm-svn: 47267

For now, avoid commuting def MI for copy MI's whose source is not killed. That simply trade a live interval for another and because only the non-two-address operands can be folded into loads, may end up pessimising code.

llvm-svn: 47262