llvm-svn: 27133

llvm-svn: 27132

false

llvm-svn: 27131

llvm-svn: 27130

llvm-svn: 27129

llvm-svn: 27128

llvm-svn: 27127

llvm-svn: 27126

llvm-svn: 27125

llvm-svn: 27124

llvm-svn: 27123

llvm-svn: 27122

llvm-svn: 27121

llvm-svn: 27120

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27118

Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.

llvm-svn: 27117

llvm-svn: 27116

llvm-svn: 27115

llvm-svn: 27114

llvm-svn: 27113

llvm-svn: 27112

llvm-svn: 27111

Cannot yet select: intrinsic %llvm.ppc.altivec.lvx

instead of this:

Cannot yet select: 0x9b047e0: v4i32,ch = INTRINSIC 0x9b04540:1, 0x9b04710, 0x9b04790, 0x9b04540

llvm-svn: 27110

llvm-svn: 27109

llvm-svn: 27108

llvm-svn: 27107

 <int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.

llvm-svn: 27106

llvm-svn: 27105

llvm-svn: 27104

llvm-svn: 27103

llvm-svn: 27102

llvm-svn: 27101

llvm-svn: 27100

llvm-svn: 27099

llvm-svn: 27098

llvm-svn: 27097

llvm-svn: 27096

llvm-svn: 27095

llvm-svn: 27094