llvm-svn: 72593

llvm-svn: 72395

llvm-svn: 72337

llvm-svn: 72336

llvm-svn: 72335

for ARM.  This fixes rdar://6908807.

llvm-svn: 72269

llvm-svn: 72172

llvm-svn: 72138

This fixes pr4233.

llvm-svn: 72115

the stack.  Patch by Sandeep Patel.

llvm-svn: 72106

llvm-svn: 72105

to run last because it needs to know the exact size and position of every
basic block.  Currently CodePlacementOpt is set up to run last.  It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.

llvm-svn: 72037

llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).

llvm-svn: 71758

llvm-svn: 71735

llvm-svn: 71726

booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722

a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.

llvm-svn: 71610

llvm-svn: 71602

llvm-svn: 71563

llvm-svn: 71562

will make it more obvious what it represents, and stop
it being confused with the StoreSize.

llvm-svn: 71349

which better identifies what the optimization is doing. And is more flexible for
future uses.

llvm-svn: 70440

Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.

llvm-svn: 70343

llvm-svn: 70275

use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

llvm-svn: 70270

f64 types.  This is not used for anything yet.

llvm-svn: 70006

between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.

llvm-svn: 69978

chained and "flagged" together.  I also made a few changes to handle the
chain and flag values more consistently.  I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).

llvm-svn: 69977

should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.

llvm-svn: 69973

in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock.  Thanks for Anton for suggesting this.

llvm-svn: 69615

llvm-svn: 69382

llvm-svn: 69381

punctuation.  No functional changes.

llvm-svn: 69378

for ARM.  Patch by Sandeep Patel.

llvm-svn: 69371

ARMTargetLowering::isLegalAddressingMode.

llvm-svn: 68619

When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545

Patch by Richard Pennington.

llvm-svn: 68464

llvm-svn: 68405

llvm-svn: 68404

assembly.

llvm-svn: 68218