llvm-svn: 198580

This moves the check up into the parent class so that all targets can use it
without having to copy (and keep in sync) the same error message.

llvm-svn: 198579

llvm-svn: 198578

llvm-svn: 198577

Move the ARM EHABI unwind opcode definitions from the ARM MCTargetDesc into LLVM
Support.  This enables sharing of the definitions across the ARM target code as
well as llvm-readobj.  This will allow implementation of the unwind decoding in
llvm-readobj.

llvm-svn: 198576

llvm-svn: 198567

Add some tests to validate correct register selection, including a fix
to an existing test which was requiring the *wrong* output.

Patch from David Woodhouse.

llvm-svn: 198566

llvm-svn: 198565

Remove opcode from MOV32r0 that I accidentally left when I converted it to Pseudo. Remove FIXME as well.

llvm-svn: 198564

Fix indentation, name registers similar to ARM ARM.

No functionality change!

llvm-svn: 198563

AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD;
Optimized a truncate pattern.

llvm-svn: 198562

section tags to the llvm-readobj.

llvm-svn: 198561

llvm-svn: 198560

Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.

llvm-svn: 198557

Missed this when adding the skeleton analysis. Caught by a build break
in the next patch I'm working on when trying to use the analysis.

llvm-svn: 198556

llvm-svn: 198552

llvm-svn: 198551

llvm-svn: 198550

llvm-svn: 198547

llvm-svn: 198546

Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.

llvm-svn: 198545

Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.

llvm-svn: 198544

Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.

llvm-svn: 198543

instructions. I needed this for a quick experiment I was making, and
while I've no idea if that will ever get committed, I didn't want to
throw away the pattern match code and for anyone else to have to write
it again. I've added unittests to make sure this works correctly.

In fun news, this also uncovered the IRBuilder bug. Doh!

llvm-svn: 198541

failed to correctly propagate the NUW and NSW flags to the constant
folder for two instructions. I've added a unittest to cover flag
propagation for the rest of the instructions and constant expressions.

llvm-svn: 198538

llvm-svn: 198537

llvm-svn: 198536

I'm adding next be a lot more readable.

llvm-svn: 198534

llvm-svn: 198533

basic block to hold instructions, and managing all of their lifetimes in
a fixture. This makes it easy to sink the expectations into the test
cases themselves which also makes things a bit more explicit and clearer
IMO.

llvm-svn: 198532

__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.

llvm-svn: 198531

Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.

llvm-svn: 198530

Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time.

llvm-svn: 198529

llvm-svn: 198528

All other uses of this macro in LLVM/clang have been moved to the function
definition so follow suite (and the usage advice) here too for consistency.

llvm-svn: 198516

Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.

llvm-svn: 198515

This commit was the source of crasher PR18384:

While deleting: label %for.cond127
An asserting value handle still pointed to this value!
UNREACHABLE executed at llvm/lib/IR/Value.cpp:671!

Reverting to get the builders green, feel free to re-land after fixing up.
(Renato has a handy isolated repro if you need it.)

This reverts commit r198478.

llvm-svn: 198503

llvm-svn: 198484

Fixes PR18356.

llvm-svn: 198480

getSCEV for an ashr instruction creates an intermediate zext
expression when it truncates its operand.

The operand is initially inside the loop, so the narrow zext
expression has a non-loop-invariant loop disposition.

LoopSimplify then runs on an outer loop, hoists the ashr operand, and
properly invalidate the SCEVs that are mapped to value.

The SCEV expression for the ashr is now an AddRec with the hoisted
value as the now loop-invariant start value.

The LoopDisposition of this wide value was properly invalidated during
LoopSimplify.

However, if we later get the ashr SCEV again, we again try to create
the intermediate zext expression. We get the same SCEV that we did
earlier, and it is still cached because it was never mapped to a
Value. When we try to create a new AddRec we abort because we're using
the old non-loop-invariant LoopDisposition.

I don't have a solution for this other than to clear LoopDisposition
when LoopSimplify hoists things.

I think the long-term strategy should be to perform LoopSimplify on
all loops before computing SCEV and before running any loop opts on
individual loops. It's possible we may want to rerun LoopSimplify on
individual loops, but it should rarely do anything, so rarely require
invalidating SCEV.

llvm-svn: 198478