into MachineInstrs. This is mostly just moving the code from
ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr
emitting from scheduling.

llvm-svn: 83699

since it won't do any folding. This will help avoid some inconvenient
casting.

llvm-svn: 83698

it isn't needed in the ScheduleDAGSDNodes schedulers.

llvm-svn: 83691

Extract scope information from the variable itself, instead of relying on alloca or llvm.dbg.declare location.

While recording beginning of a function, use scope info from the first location entry instead of just relying on first location entry itself.

llvm-svn: 83684

similar to getTargetExtractSubreg.

llvm-svn: 83564

This is not yet enabled.

llvm-svn: 83400

This code is not  yet enabled.

llvm-svn: 83349

If location info is attached with an instruction then keep track of alloca slots used by a variable. This info will be used by AsmPrinter to emit debug info for variables.

llvm-svn: 83189

llvm-svn: 83182

llvm-svn: 83164

basic blocks that are so long that their size overflows a short.

Also assert that overflow does not happen in the future, as requested by Evan.

This fixes PR4401.

llvm-svn: 83159

Remove unnecessary cast.

llvm-svn: 83100

llvm-svn: 83019

llvm-svn: 83016

llvm-svn: 82995

where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. 

llvm-svn: 82861

 - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794

naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790

before producing FSIN, FCOS, FSQRT.  If they aren't
so marked we have to assume they might set errno.

llvm-svn: 82781

allows appropriate backends to generate a sqrt instruction.

On x86, this isn't done at -O0 because we go through
FastISel instead.  This is a behavior change from before
this series of sqrt patches started.  I think this is OK
considering that compile speed is most important at -O0, but
could be convinced otherwise.

llvm-svn: 82778

Previously, it treated GV+28 GV+0 as different bases, and assumed they could
not alias.

llvm-svn: 82753

llvm-svn: 82742

llvm-svn: 82656

is also the name of their type, as declarations like "EVT EVT" look
really odd.

llvm-svn: 82654

two different places for printing MachineMemOperands.

Drop the virtual from Value::dump and instead give Value a
protected virtual hook that can be overridden by subclasses
to implement custom printing. This lets printing be more
consistent, and simplifies printing of PseudoSourceValue
values.

llvm-svn: 82599

the base pointer, without the offset. This matches MemSDNode's
new alignment behavior, and holds more interesting information.

llvm-svn: 82473

llvm-svn: 82397

llvm-svn: 82355

Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.

llvm-svn: 82311

Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273

llvm-svn: 82245

llvm-svn: 82215

Fix a bug in sdisel switch lowering code. When it updates the phi nodes in switch successor blocks, it can introduce multiple phi operands of the same value from different blocks (and may not be on the predecessor list).

This can be seen on CodeGen/Generic/2006-09-06-SwitchLowering.ll. But it's not known to cause any real regression (but I have added an assertion for it now).

llvm-svn: 82214

64-bit systems.

llvm-svn: 82180

llvm-svn: 82080

llvm-svn: 82077

SVOffsets.

llvm-svn: 81937

Better solution for tracking both the original alignment of the access, and the current alignment based
on the source value offset.  This avoids increasing the size of mem nodes. 

llvm-svn: 81897

llvm-svn: 81819

1. Switch from an std::set to a SmallPtrSet for visited chain nodes.
2. Do not force the recursive flattening of token factor nodes, regardless of
   use count.
3. Immediately process newly created TokenFactor nodes.

Also, improve combiner-aa by teaching it that loads to non-overlapping offsets
of relatively aligned objects cannot alias.

These changes result in a >5x speedup for combiner-aa on most testcases.

llvm-svn: 81816