llvm-svn: 139013

llvm-svn: 139012

llvm-svn: 139010

This changes loop unrolling to use the same mechanism for trip count
computation as indvars. This is a stronger check that tends to unroll
more loops. A very common side-effect is that many single iteration
loops will be removed sooner. The real goal was simply to remove
dependence on canonical IVs.

x86 is break even.
ARM performance changes to expect (+ is good):
External/SPEC/CFP2000/183.equake/183.equake +13%
SingleSource/Benchmarks/Dhrystone/fldry     +21%
MultiSource/Applications/spiff/spiff         +3%
SingleSource/Benchmarks/Stanford/Puzzle     -14%

The Puzzle regression is actually an improvement in loop optimization
that defeats GVN: rdar://problem/10065079.

llvm-svn: 139009

llvm-svn: 139008

ConstantVector.

llvm-svn: 139007

This fixes PR10813.

llvm-svn: 139006

will be valid. This fixes PR10820.

llvm-svn: 139005

llvm-svn: 139004

Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.

llvm-svn: 138997

Perform the upgrading in steps.

* First, create a map of the invokes to the EH intrinsics.

* Next, take that mapping and determine if the invoke's unwind destination has a
  single predecessor. If not, then create a new empty block to hold the new
  landingpad instruction.

* Create a landingpad instruction into the uwnind destination. Fill it with the
  values from the old selector. Map the old intrinsic calls to the new
  landingpad values (there may be multiple landingpad instructions per instrinic
  call pairs).

* Go through the old intrinsic calls, create a PHI node when necessary, and then
  replace their values with the new values from the landingpad instructions.

* Delete all dead instructions.

* ???

* Profit!

llvm-svn: 138990

llvm-svn: 138989

llvm-svn: 138982

llvm-svn: 138980

to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977

- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976

llvm-svn: 138974

Fix apparent build error caused by r138948 on certain versions of GCC with -Werror. Sorry for the inconvenience.

llvm-svn: 138973

llvm-svn: 138968

Duncan noticed this!

llvm-svn: 138967

llvm-svn: 138966

Fix an issue with the IR sink pass found by inspection.  (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.)

llvm-svn: 138965

llvm-svn: 138964

Remove broken emacs mode major notation marking a C++ file as C.
No functionality change.

llvm-svn: 138963

Make isSafeToSpeculativelyExecute() return the right answer for some new instructions.  Found by inspection; not sure what practical impact, if any, this has.

llvm-svn: 138962

llvm-svn: 138955

llvm-svn: 138954

An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

llvm-svn: 138953

llvm-svn: 138952

only one use. Fix PR10825.

llvm-svn: 138951

llvm-svn: 138948

llvm-svn: 138946

The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.

<rdar://problem/10032939>

llvm-svn: 138945

An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944

Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690

llvm-svn: 138934

llvm-svn: 138933

Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are.

llvm-svn: 138932

llvm-svn: 138931

The landingpad instruction can be removed only when its invokes are removed.

llvm-svn: 138930

llvm-svn: 138928