llvm-svn: 113965

was the main putative user of the binding is actually maintaining its own
different binding, see http://git.ada.cx/cgi-bin/cgit.cgi/draco.git/

llvm-svn: 113960

The problem was that the test for whether a compiler supports it or not was
inaccurate, but has to be accurate: LLVM_LOCAL_VISIBILITY is an optimization
and not needed for correctness, so wrongly thinking a compiler doesn't support
it is not a big deal, but LLVM_GLOBAL_VISIBILITY is for correctness, and not
an optimization: getting it wrong is fatal: it needs to be set based on a
configure test not testing the gcc version.  Since dragonegg has moved to a
different scheme, and it was the only user of LLVM_GLOBAL_VISIBILITY, just
remove this macro.

llvm-svn: 113959

wraps up r8418316

llvm-svn: 113949

for call.  Add this.

llvm-svn: 113948

even in 64-bit mode apparently.

llvm-svn: 113945

add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316

llvm-svn: 113938

llvm-svn: 113937

llvm-svn: 113936

version because it adds a prefix and makes even less sense
than the other broken forms.  This wraps up rdar://8431422

llvm-svn: 113932

llvm-svn: 113930

rdar://8431422

llvm-svn: 113929

llvm-svn: 113928

llvm-svn: 113927

llvm-svn: 113926

exposed to config files.

llvm-svn: 113923

alliterate.

llvm-svn: 113922

instead of crashing.  This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present

llvm-svn: 113921

functions, since int64 is not a legal type and using it leads to inefficient
code.  PR8036.

llvm-svn: 113919

storeRegToStackSlot.

llvm-svn: 113918

llvm-svn: 113915

llvm-svn: 113914

attribute(used).

llvm-svn: 113911

"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."

Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.

llvm-svn: 113903

This fixes PR8114

llvm-svn: 113894

llvm-svn: 113892

that needs to be shared a bit more widely around.

llvm-svn: 113886

change.

llvm-svn: 113878

llvm-svn: 113877

llvm-svn: 113876

get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).

llvm-svn: 113875

llvm-svn: 113867

llvm-svn: 113865

llvm-svn: 113860

llvm-svn: 113859

isn't a good level of abstraction for memdep. Instead, generalize
AliasAnalysis::alias and related interfaces with a new Location
class for describing a memory location. For now, this is the same
Pointer and Size as before, plus an additional field for a TBAA tag.

Also, introduce a fixed MD_tbaa metadata tag kind.

llvm-svn: 113858

llvm-svn: 113857

llvm-svn: 113856

llvm-svn: 113855

an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4).  Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.

llvm-svn: 113854