to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.

llvm-svn: 62194

llvm-svn: 62180

llvm-svn: 62179

llvm-svn: 62174

sees attributes it doesn't know.

llvm-svn: 62155

Use DebugInfo interface to lower dbg_* intrinsics.

llvm-svn: 62127

suggested by Chris.

llvm-svn: 62099

llvm-svn: 62024

llvm-svn: 61991

llvm-svn: 61972

the same formatting as their corresponding SSE2 instructions, for
consistency.

llvm-svn: 61971

Convert DwarfWriter into a pass.
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.

llvm-svn: 61955

llvm-svn: 61918

llvm-svn: 61917

The error was reported by gcc-4.3.0 during compilation.

llvm-svn: 61896

into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.

llvm-svn: 61842

llvm-svn: 61841

llvm-svn: 61836

X86_COND_B and X86_COND_AE, respectively.

llvm-svn: 61835

converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
   movl  %esi, %edi
   inc   %edi
with this:
   lea   1(%rsi), %edi
which appears to be beneficial.

llvm-svn: 61830

- Add preliminary support for v2i32; load/store generates the right code but
  there's a lot work to be done to make this vector type operational.

llvm-svn: 61829

llvm-svn: 61785

- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we
  need to ensure that i128 is 16-byte aligned in real life), and 128 zero-
  extends are supported.
- New td file: SPU128InstrInfo.td: this is where all new i128 support should
  be put in the future.
- Continue to hammer on i64 operations and test cases; ensure that the only
  remaining problem will be i64 mul.

llvm-svn: 61784

llvm-svn: 61765

llvm-svn: 61715

squash warnings.

llvm-svn: 61707

llvm-svn: 61686

- Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests
  accordingly.

llvm-svn: 61672

- Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ.
- Kill unused/unnecessary nodes in SPUNodes.td
- Beef out the i64operations.c test harness to use a lot of unaligned
  loads, test loops and LLVM loop/basic block optimizations; run the
  test harness successfully on real Cell hardware.

llvm-svn: 61664

llvm-svn: 61603

llvm-svn: 61602

- Remove custom lowering for BRCOND
- Add remaining functionality for branches in SPUInstrInfo, such as branch
  condition reversal and load/store folding. Updated BrCond test to reflect
  branch reversal.

llvm-svn: 61597

  register copies a little easier to pick out from the output.
- Fix bug 3192.

llvm-svn: 61591

Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.

llvm-svn: 61557

llvm-svn: 61556

Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory.

llvm-svn: 61555

promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).

llvm-svn: 61542

llvm-svn: 61513

  instruction sequence and cannot ordinarily be simplified by DAGcombine
  into the various target description files or SPUDAGToDAGISel.cpp.

  This makes some 64-bit operations legal.

- Eliminate target-dependent ISD enums.

- Update tests.

llvm-svn: 61508

Darwin doesn't. Make this optional for platforms.

llvm-svn: 61484