- Apr 16, 2013
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Nadav Rotem authored
SLPVectorizer: Make it a function pass and add code for hoisting the vector-gather sequence out of loops. llvm-svn: 179562
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- Apr 15, 2013
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Rafael Espindola authored
llvm-svn: 179551
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Rafael Espindola authored
Looks like it was evaluating undef == undef to true. llvm-svn: 179549
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Tom Stellard authored
Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
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Tom Stellard authored
llvm-svn: 179545
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Tom Stellard authored
llvm-svn: 179544
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Jim Grosbach authored
llvm-svn: 179542
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Jim Grosbach authored
llvm-svn: 179541
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John Criswell authored
No content changes. llvm-svn: 179540
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Rafael Espindola authored
llvm-svn: 179536
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Arnold Schwaighofer authored
Patch by Cameron McInally <cameron.mcinally@nyu.edu>. llvm-svn: 179535
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Rafael Espindola authored
llvm-svn: 179534
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Tim Northover authored
llvm-svn: 179532
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Rafael Espindola authored
llvm-svn: 179530
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Rafael Espindola authored
I will remove the isBigEndianHost function once I update clang. The ifdef logic is designed to * not use configure/cmake to avoid breaking -arch i686 -arch ppc. * default to little endian * be as small as possible It looks like sys/endian.h is the preferred header on most modern BSD systems, but it is better to change this in a followup patch as machine/endian.h is available on FreeBSD, OpenBSD, NetBSD and OS X. llvm-svn: 179527
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Andy Gibbs authored
This is a rework of the broken parts in r179373 which were subsequently reverted in r179374 due to incompatibility with C++98 compilers. This version should be ok under C++98. llvm-svn: 179520
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Tim Northover authored
llvm-svn: 179518
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Eric Christopher authored
I can fix the testcases here: http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/6952 This reverts commit r179512 due to testcases specifying triples that they didn't actually mean and causing failures on other platforms. llvm-svn: 179513
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Eric Christopher authored
llvm-svn: 179512
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Nadav Rotem authored
llvm-svn: 179511
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Nadav Rotem authored
Docs: merge the description of the BB and SLP vectorizers and document the -fslp-vectorize-aggressive flag. llvm-svn: 179510
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Nadav Rotem authored
Add an option -vectorize-slp-aggressive for running the BB vectorizer. Make -fslp-vectorize run the slp-vectorizer. llvm-svn: 179508
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Nadav Rotem authored
llvm-svn: 179505
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Nadav Rotem authored
llvm-svn: 179504
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Jia Liu authored
llvm-svn: 179503
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Hal Finkel authored
Now that the CR spilling issues have been resolved, we can remove the unmodeled-side-effect attributes from the comparison instructions (and also mark them as isCompare). By allowing these, by default, to have unmodeled side effects, we were hiding problems with CR spilling; but everything seems much happier now. llvm-svn: 179502
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Hal Finkel authored
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). llvm-svn: 179500
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Eric Christopher authored
This reverts commit r179497 and the accompanying commit as it broke random platforms that aren't osx. llvm-svn: 179499
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Eric Christopher authored
llvm-svn: 179498
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Eric Christopher authored
and use that as the default triple for the module and target data layout. llvm-svn: 179497
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- Apr 14, 2013
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Nico Rieck authored
llvm-svn: 179494
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David Majnemer authored
One performs: (X == 13 | X == 14) -> X-13 <u 2 The other: (A == C1 || A == C2) -> (A & ~(C1 ^ C2)) == C1 The problem is that there are certain values of C1 and C2 that trigger both transforms but the first one blocks out the second, this generates suboptimal code. Reordering the transforms should be better in every case and allows us to do interesting stuff like turn: %shr = lshr i32 %X, 4 %and = and i32 %shr, 15 %add = add i32 %and, -14 %tobool = icmp ne i32 %add, 0 into: %and = and i32 %X, 240 %tobool = icmp ne i32 %and, 224 llvm-svn: 179493
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Nadav Rotem authored
llvm-svn: 179492
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Benjamin Kramer authored
llvm-svn: 179483
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Nadav Rotem authored
llvm-svn: 179480
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Nadav Rotem authored
llvm-svn: 179479
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Nadav Rotem authored
llvm-svn: 179478
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Jakob Stoklund Olesen authored
Test case by llvm-stress. llvm-svn: 179477
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Nadav Rotem authored
llvm-svn: 179476
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Nadav Rotem authored
SLPVectorizer: Add support for trees that don't start at binary operators, and add the cost of extracting values from the roots of the tree. llvm-svn: 179475
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