llvm-svn: 77945

llvm-svn: 77944

reset the current analysis context of the AnalysisManager.

llvm-svn: 77943

Thanks to Eli Friedman for noticing it.

llvm-svn: 77942

ProgramPoints. ProgramPoints will refer to them in the furture.

llvm-svn: 77941

Fixes PR4669

llvm-svn: 77940

Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.

llvm-svn: 77939

options, which don't appear to be useful.  -enable-mips-absolute-call is
completely unused (and unless I'm mistaken, is supposed to have the 
same effect that -relocation-model=dynamic-no-pic should have), 
and -disable-mips-abicall appears to be effectively a 
synonym for -relocation-model=static. Adjust the few users of hasABICall
to checks which seem more appropriate.  Update MipsSubtarget, 
MipsTargetMachine, and MipselTargetMachine to synchronize with recent 
changes.

llvm-svn: 77938

llvm-svn: 77937

llvm-svn: 77936

 - Patch by Jonathan Gray!

llvm-svn: 77935

llvm-svn: 77934

llvm-svn: 77933

llvm-svn: 77932

llvm-svn: 77931

- Tidy up some headers.

llvm-svn: 77929

llvm-svn: 77928

 - The C, C++, MSIL, and Mips backends still need the module.

llvm-svn: 77927

llvm-svn: 77926

template partial specialization. Then, use those template arguments
when instantiating members of that class template partial
specialization. Fixes PR4607.

llvm-svn: 77925

llvm-svn: 77920

pushes in the function prolog if the function doesn't have any stack space,
i.e. for a prolog like:

0x40011870:     push %r15
0x40011872:     push %r14
0x40011874:     push %rbx

Patch by Zoltan!

llvm-svn: 77919

Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918

__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.

__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.

We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.

llvm-svn: 77917

llvm-svn: 77916

llvm-svn: 77915

llvm-svn: 77914

llvm-svn: 77913

llvm-svn: 77912

llvm-svn: 77911

llvm-svn: 77910

llvm-svn: 77909

match.

llvm-svn: 77908

llvm-svn: 77907

llvm-svn: 77906

llvm-svn: 77905

Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier.
Allow redefinition of a sub-register of a live register.

llvm-svn: 77904

llvm-svn: 77903

This is just the framework to identify the needed workarounds. They are not actually implemented.

llvm-svn: 77902

llvm-svn: 77901