llvm-svn: 123405

the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.

With this, we can properly pretty-print and encode assembly like:
	mrc p15, #0, r3, c13, c0, #3

Fixes <rdar://problem/8857858>.

llvm-svn: 123404

llvm-svn: 123399

llvm-svn: 123397

directional local labels like 1f and 2b.

llvm-svn: 123393

set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456

llvm-svn: 123387

in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369

16 bytes for PR8969. Update all testcases accordingly.

llvm-svn: 123367

.code 32 if the TargetMachine's isThumb() boolean does not match.  The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.

llvm-svn: 123353

llvm-svn: 123350

llvm-svn: 123341

that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340

enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321

of the switch block to appease GCC.

llvm-svn: 123317

llvm-svn: 123315

llvm-svn: 123310

ensure %o7 is not assigned as the destination of getpcx instruction.

llvm-svn: 123304

are correctly marked as used instead of passing all possible argument registers
as used.  

llvm-svn: 123301

llvm-svn: 123297

  R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294

.s Test added.

llvm-svn: 123292

llvm-svn: 123281

llvm-svn: 123276

llvm-svn: 123253

llvm-svn: 123246

llvm-svn: 123242

McARM: Sketch some logic for determining when to add carry set and predication code operands based on the "canonical mnemonic".

llvm-svn: 123239

carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

llvm-svn: 123238

llvm-svn: 123229

Filling no-ops is done just before emitting of assembly,
when the instruction stream is final. No-ops are inserted
to align the instructions so the dual-issue of the pipeline
is utilized. This speeds up generated code with a minimum of 
1% on a select set of algorithms.

This pass may be redundant if the instruction scheduler and 
all subsequent passes that modify the instruction stream 
(prolog+epilog inserter, register scavenger, are there others?)
are made aware of the instruction alignments.

llvm-svn: 123226

point values to their integer representation through the SSE intrinsic
calls. This is the last part of a README.txt entry for which I have real
world examples.

llvm-svn: 123206

Fix a random missed optimization by making InstCombine more aggressive when determining which bits are demanded by
a comparison against a constant.

llvm-svn: 123203

restore the stack pointer from the frame pointer on thumbv6.

Fixes rdar://8819685

llvm-svn: 123196

llvm-svn: 123193

operation in some cases.

llvm-svn: 123190

llvm-svn: 123189

instructions but are restricted pseudo forms.

llvm-svn: 123177

instructions but are restricted pseudo forms.

llvm-svn: 123176

llvm-svn: 123175

llvm-svn: 123172