Commits · b9e47a8cd0c648422d401d6620130bf06c60fc6f · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jul 23, 2016
- [X86][SSE] Added tests where we should be trying to widen a load+splat into a broadcast · b9e47a8c
  Simon Pilgrim authored Jul 23, 2016
  b9e47a8c
- [X86][SSE] Regenerated uitofp <2 x i32> -> <2 x float> conversion tests · 8aa6f344
  Simon Pilgrim authored Jul 23, 2016
  8aa6f344
- [AVX512] Implement commuting support for EVEX encoded FMA3 instructions. · b6519db9
  Craig Topper authored Jul 23, 2016
  b6519db9
- Revert "[AMDGPU] Emit read-only data to .rodata for hsa" · b8253c88
  Tom Stellard authored Jul 22, 2016
  b8253c88
- GlobalISel: allow multiple types on MachineInstrs. · 98a56eb7
  Tim Northover authored Jul 22, 2016
  98a56eb7
Jul 22, 2016
- GlobalISel: implement legalization pass, with just one transformation. · 33b07d67
  Tim Northover authored Jul 22, 2016
  33b07d67
- Invariant start/end intrinsics overloaded for address space · 0be4a0e6
  Anna Thomas authored Jul 22, 2016
  0be4a0e6
- AMDGPU: Remove redundant test · e2fe67b9
  Matt Arsenault authored Jul 22, 2016
  e2fe67b9
- AMDGPU: Fix groupstaticsize for large LDS · 3c07c813
  Matt Arsenault authored Jul 22, 2016
  3c07c813
- AMDGPU: Add HSA dispatch id intrinsic · 8d718dcf
  Matt Arsenault authored Jul 22, 2016
  8d718dcf
- AMDGPU: Fix i1 fp_to_int · 7fb961f3
  Matt Arsenault authored Jul 22, 2016
  7fb961f3
- GlobalISel: implement alloca instruction · bd505460
  Tim Northover authored Jul 22, 2016
  bd505460
- [SelectionDAG] Optimization of BITREVERSE legalization for power-of-2 integer scalar/vector types · 820f87a7
  Simon Pilgrim authored Jul 22, 2016
  820f87a7
- [Hexagon] Use loop data prefetch on Hexagon · d3d0a4bd
  Krzysztof Parzyszek authored Jul 22, 2016
  d3d0a4bd
- [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128 (reapplied) · ea0d4f99
  Simon Pilgrim authored Jul 22, 2016
  ea0d4f99
- [FastISel] Ignore @llvm.assume. · 29333c9d
  Ahmed Bougacha authored Jul 22, 2016
  29333c9d
- Revert "[X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128" · 5ba0e203
  Benjamin Kramer authored Jul 22, 2016
  5ba0e203
- [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions · 2db00ce4
  Hrvoje Varga authored Jul 22, 2016
  2db00ce4
- [AVX512] Add ExeDomain to vector extend and truncate instructions. · 52e2e838
  Craig Topper authored Jul 22, 2016
  52e2e838
- [AVX512] Add initial support for the Execution Domain fixing pass to change some EVEX instructions. · f4151bea
  Craig Topper authored Jul 22, 2016
  f4151bea
- [AVX512] Add load folding for some AVX512VL logic and arithmetic instructions. · 0b90756b
  Craig Topper authored Jul 22, 2016
  0b90756b
- [AVX512] Update X86InstrInfo::foldMemoryOperandCustom to handle the EVEX encoded instructions too. · ab13b33d
  Craig Topper authored Jul 22, 2016
  ab13b33d
- [MIRTesting] Abort when failing to parse a function. · ecd81a3d
  Quentin Colombet authored Jul 21, 2016
  ecd81a3d
- [X86] Do not use AND8ri8 in AVX512 pattern · c523333b
  Michael Kuperstein authored Jul 21, 2016
  c523333b
Jul 21, 2016
- [AArch64][Inline-Asm] Return the 32-bit floating point register class · b8d2873d
  Akira Hatanaka authored Jul 21, 2016
  b8d2873d
- Revert "Invariant start/end intrinsics overloaded for address space" · c858faa2
  Anna Thomas authored Jul 21, 2016
  c858faa2
- Invariant start/end intrinsics overloaded for address space · 29b24dfe
  Anna Thomas authored Jul 21, 2016
  29b24dfe
- [IRTranslator] Add G_SUB opcode. · 2b59eab7
  Quentin Colombet authored Jul 21, 2016
  2b59eab7
- [AMDGPU] Emit read-only data to .rodata for hsa · 3c0d8d22
  Konstantin Zhuravlyov authored Jul 21, 2016
  3c0d8d22
- [IRTranslator] Add G_AND opcode. · 7bcc921d
  Quentin Colombet authored Jul 21, 2016
  7bcc921d
- [AArch64] Load/store opt: Don't count transient instructions towards search limits. · 4ff2e36d
  Geoff Berry authored Jul 21, 2016
  4ff2e36d
- [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element · 88e0940d
  Simon Pilgrim authored Jul 21, 2016
  88e0940d
- Fixed line endings · 4caefdf8
  Simon Pilgrim authored Jul 21, 2016
  4caefdf8
- [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128 · c8e20b11
  Simon Pilgrim authored Jul 21, 2016
  c8e20b11
- ExecutionDepsFix - Fix bug in clearance calculation · c1fa1633
  Marina Yatsina authored Jul 21, 2016
  c1fa1633
- AMDGPU: Fix phis from blocks split due to register indexing · f0ba86a4
  Matt Arsenault authored Jul 21, 2016
  f0ba86a4
- IPRA: Fix RegMask calculation for alias registers · d9fdad72
  Matthias Braun authored Jul 21, 2016
  d9fdad72
- [NVPTX] Enable the load-store vectorizer on nvptx. · cd564c6b
  Justin Lebar authored Jul 20, 2016
  cd564c6b
Jul 20, 2016
- [NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC. · 7e9c9a65
  Artem Belevich authored Jul 20, 2016
  7e9c9a65
- [AArch64][FastISel] Select -O0 legal cmpxchg. · a0cdd790
  Ahmed Bougacha authored Jul 20, 2016
  a0cdd790