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  1. Jun 28, 2012
    • Jack Carter's avatar
      This allows hello world to be compiled for Mips 64 direct object. · b9f9de93
      Jack Carter authored
      It takes advantage of r159299 which introduces relocation support for N64. 
      elf-dump needed to be upgraded to support N64 relocations as well.
      
      This passes make check.
      
      Jack
      
      llvm-svn: 159301
      b9f9de93
    • Chad Rosier's avatar
      Whitespace. · 51afe639
      Chad Rosier authored
      llvm-svn: 159300
      51afe639
    • Jack Carter's avatar
      The ELF relocation record format is different for N64 · 8ad0c272
      Jack Carter authored
      which many Mips 64 ABIs use than for O64 which many 
      if not all other target ABIs use.
      
      Most architectures have the following 64 bit relocation record format:
      
        typedef struct
        {
          Elf64_Addr   r_offset; /* Address of reference */
          Elf64_Xword  r_info;   /* Symbol index and type of relocation */
        } Elf64_Rel;
      
        typedef struct
        {
          Elf64_Addr    r_offset;
          Elf64_Xword   r_info;
          Elf64_Sxword  r_addend;
        } Elf64_Rela;
      
      Whereas N64 has the following format:
      
        typedef struct
        {
          Elf64_Addr    r_offset;/* Address of reference */
          Elf64_Word  r_sym;     /* Symbol index */
          Elf64_Byte  r_ssym;    /* Special symbol */
          Elf64_Byte  r_type3;   /* Relocation type */
          Elf64_Byte  r_type2;   /* Relocation type */
          Elf64_Byte  r_type;    /* Relocation type */
        } Elf64_Rel;
      
        typedef struct
        {
          Elf64_Addr    r_offset;/* Address of reference */
          Elf64_Word  r_sym;     /* Symbol index */
          Elf64_Byte  r_ssym;    /* Special symbol */
          Elf64_Byte  r_type3;   /* Relocation type */
          Elf64_Byte  r_type2;   /* Relocation type */
          Elf64_Byte  r_type;    /* Relocation type */
          Elf64_Sxword  r_addend;
        } Elf64_Rela;
      
      The structure is the same size, but the r_info data element 
      is now 5 separate elements. Besides the content aspects, 
      endian byte reordering will be different for the area with 
      each element being endianized separately.
      
      I treat this as generic and continue to pass r_type as 
      an integer masking and unmasking the byte sized N64 
      values for N64 mode. I've implemented this and it causes no 
      affect on other current targets.
      
      This passes make check.
      
      Jack
      
      llvm-svn: 159299
      8ad0c272
  2. Jun 27, 2012
  3. Jun 26, 2012
    • Manman Ren's avatar
      X86: add GATHER intrinsics (AVX2) in LLVM · a0982041
      Manman Ren authored
      Support the following intrinsics:
      llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
      llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
      llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
      llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
      
      Modified Disassembler to handle VSIB addressing mode.
      
      llvm-svn: 159221
      a0982041
    • Jack Carter's avatar
      There are a number of generic inline asm operand modifiers that · 5e69cffe
      Jack Carter authored
      up to r158925 were handled as processor specific. Making them 
      generic and putting tests for these modifiers in the CodeGen/Generic
      directory caused a number of targets to fail. 
      
      This commit addresses that problem by having the targets call 
      the generic routine for generic modifiers that they don't currently
      have explicit code for.
      
      For now only generic print operands 'c' and 'n' are supported.vi
      
      
      Affected files:
      
          test/CodeGen/Generic/asm-large-immediate.ll
          lib/Target/PowerPC/PPCAsmPrinter.cpp
          lib/Target/NVPTX/NVPTXAsmPrinter.cpp
          lib/Target/ARM/ARMAsmPrinter.cpp
          lib/Target/XCore/XCoreAsmPrinter.cpp
          lib/Target/X86/X86AsmPrinter.cpp
          lib/Target/Hexagon/HexagonAsmPrinter.cpp
          lib/Target/CellSPU/SPUAsmPrinter.cpp
          lib/Target/Sparc/SparcAsmPrinter.cpp
          lib/Target/MBlaze/MBlazeAsmPrinter.cpp
          lib/Target/Mips/MipsAsmPrinter.cpp
          
      MSP430 isn't represented because it did not even run with
      the long existing 'c' modifier and it was not apparent what
      needs to be done to get it inline asm ready.
      
      Contributer: Jack Carter
      llvm-svn: 159203
      5e69cffe
    • Elena Demikhovsky's avatar
      Removed unused variable · 863d2d32
      Elena Demikhovsky authored
      llvm-svn: 159197
      863d2d32
    • Bill Wendling's avatar
      Rename to match other X86_64* names. · 8ed44466
      Bill Wendling authored
      llvm-svn: 159196
      8ed44466
    • Elena Demikhovsky's avatar
      Shuffle optimization for AVX/AVX2. · 26088d2e
      Elena Demikhovsky authored
      The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction.
      Before:
            vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3]
             vpermilps       $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3]
             vextractf128    $1, %ymm1, %xmm1
             vextractf128    $1, %ymm0, %xmm0
             vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3]
             vpermilps       $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3]
             vinsertf128     $1, %xmm0, %ymm2, %ymm0
      After:
            vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4]
            vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4]
            vunpcklps       %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
      
      llvm-svn: 159188
      26088d2e
    • Craig Topper's avatar
      Remove some duplicate instructions that exist only to given different... · 94bf0f38
      Craig Topper authored
      Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead.
      
      llvm-svn: 159184
      94bf0f38
    • Eli Friedman's avatar
      Make some ugly hacks for inline asm operands which name a specific register a... · bbcd09cc
      Eli Friedman authored
      Make some ugly hacks for inline asm operands which name a specific register a bit more thorough.  PR13196.
      
      llvm-svn: 159176
      bbcd09cc
  4. Jun 25, 2012
  5. Jun 24, 2012
  6. Jun 23, 2012
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