instructions and InstAliases.  Start creating InstructionInfo's
for Aliases.

llvm-svn: 117898

in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897

member, and make isAssemblerInstruction() a method (pushing some code
around inside it).

llvm-svn: 117895

todo: the result field.

llvm-svn: 117894

CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893

llvm-svn: 117892

simplify CodeGenInstruction. No functionality change.

llvm-svn: 117891

llvm-svn: 117890

instead of strings, simplifying it.

llvm-svn: 117889

argument passing.  Consolidate all SingletonRegister detection
and handling into a new 
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about.  No change in generated .inc files.

llvm-svn: 117888

CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.

llvm-svn: 117886

this can start rejecting instructions.

llvm-svn: 117885

various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884

Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862

and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861

got a dulicated line).

llvm-svn: 117860

llvm-svn: 117859

Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858

AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping.  No functionality change.

llvm-svn: 117845

that are only used by MnemonicAliases will be found.

llvm-svn: 117844

cases that are currently exercised).  Thanks to Frits van Bommel for
the great review!

llvm-svn: 117840

"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831

directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830

llvm-svn: 117828

with a useful error message instead of having tblgen explode with an 
assert.

llvm-svn: 117827

inline into MatchInstructionImpl.

llvm-svn: 117826

just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815

llvm-svn: 117724

(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606

llvm-svn: 116069

llvm-svn: 113198

llvm-svn: 113197

is busted for all variants, report it as the location.  This allows
us to get the operand right for bugs like:

t.s:3:12: error: invalid operand for instruction
	outb %al, %gs
	          ^

Even though there are reg/imm and reg/reg forms of this instruction.

llvm-svn: 113183

of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178

give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"

llvm-svn: 113176

llvm-svn: 113174

llvm-svn: 113173

llvm-svn: 113172

by doing a binary search over the mnemonic instead of doing a linear
search through all possible instructions.  This implements rdar://7785064

llvm-svn: 113171

MatchInstructionImpl. This makes it easier to read/understand
MatchInstructionImpl.

llvm-svn: 113170