give them individual stack slots once the are actually spilled.

llvm-svn: 117945

When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.

llvm-svn: 117944

llvm-svn: 117941

llvm-svn: 117940

llvm-svn: 117939

llvm-svn: 117938

llvm-svn: 117937

llvm-svn: 117936

llvm-svn: 117935

llvm-svn: 117932

codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931

llvm-svn: 117930

llvm-svn: 117929

llvm-svn: 117927

llvm-svn: 117925

patterns as such

llvm-svn: 117923

llvm-svn: 117922

llvm-svn: 117911

*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906

peephole optimizer is disabled. That's not good at all.

llvm-svn: 117905

llvm-svn: 117904

llvm-svn: 117903

must be 8 bits.  Support this memory form.

llvm-svn: 117902

aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901

llvm-svn: 117900

represents InstAliases as well.  Rename 
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).

llvm-svn: 117899

instructions and InstAliases.  Start creating InstructionInfo's
for Aliases.

llvm-svn: 117898

in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897

member, and make isAssemblerInstruction() a method (pushing some code
around inside it).

llvm-svn: 117895

todo: the result field.

llvm-svn: 117894

CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893

llvm-svn: 117892

simplify CodeGenInstruction. No functionality change.

llvm-svn: 117891

llvm-svn: 117890

instead of strings, simplifying it.

llvm-svn: 117889

argument passing.  Consolidate all SingletonRegister detection
and handling into a new 
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about.  No change in generated .inc files.

llvm-svn: 117888

CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.

llvm-svn: 117886

this can start rejecting instructions.

llvm-svn: 117885

various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884

specializations provided here. This is a little annoying because its size
changes from platform to platform. If possible, I may follow up with a patch
that uses standard constants to simplify much of this, but assuming for now
that was avoided for a reason.

llvm-svn: 117880