llvm-svn: 110543

relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.

This pass is will eventually be folded into the Machine CSE pass.

llvm-svn: 110539

form of CMPSD (etc.)  Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.)  8193553.

llvm-svn: 110491

llvm-svn: 110480

llvm-svn: 110468

implementation of the function is equivalent, so no need to provide
the target-specific version until/unless it needs to do something.

llvm-svn: 110465

llvm-svn: 110460

Without this what was happening was:

* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong

llvm-svn: 110446

llvm-svn: 110427

llvm-svn: 110425

This pass tries to remove comparison instructions when possible. For instance,
if you have this code:

   sub r1, 1
   cmp r1, 0
   bz  L1

and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.

llvm-svn: 110423

llvm-svn: 110410

llvm-svn: 110404

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

to IntrReadWriteArgMem, as it's for reading as well as writing.

llvm-svn: 110395

Support very basic (doesn't include ABI support in the front-end, varags, ...) 256-bit argument passing and return for AVX

llvm-svn: 110394

llvm-svn: 110371

llvm-svn: 110369

register for local access when it's closer to the stack slot being refererenced
than the stack pointer. Make sure to take into account any argument frame
SP adjustments that are in affect at the time.

rdar://8256090

llvm-svn: 110366

llvm-svn: 110363

Partial fix for PR7792.

llvm-svn: 110361

instructions.

llvm-svn: 110360

llvm-svn: 110359

Partial fix for PR7792.

llvm-svn: 110358

preserves the existing behavior, as it seems a concious choice to allow RS to
be null and BigStack marked true.

llvm-svn: 110307

llvm-svn: 110292

uses.

llvm-svn: 110274

llvm-svn: 110269

llvm-svn: 110268

llvm-svn: 110267

llvm-svn: 110259

simplify the call frame pseudo instructions. In that situation, the
calculations for estimating the stack size will be way off, leading to
not having an emergency spill slot when we need one. It should be possible
to be more precise about tracking the adjustment values, but not really
necessary for correctness. Upcoming cleanups for PEI in general will
render that moot.

llvm-svn: 110258

llvm-svn: 110256

See PR5201. There is no way to know if direct calls will be within the allowed
range for BL. Hence emit all calls as indirect when in JIT mode.
Without this long-running applications will fail to JIT on PowerPC with a
relocation failure.

llvm-svn: 110246

seem to be working correctly.  No functional change.

llvm-svn: 110226

llvm-svn: 110224

llvm-svn: 110200

store for "half vectors"

llvm-svn: 110198

- The COFF backend doesn't support MingW/Cygwin at the moment, it'll report an
  error, but it's still much better than random assertions from the MachO backend.
- We want to make ELF the default eventually, it's what the majority of targets use.

llvm-svn: 110197

"The CWriter::GetValueName() method does not check if a value as an alias 
and emits the alias name which will never be defined in the output .c 
file (so the output file fails to compile). This can happen if you have 
multiple inheritance with several destructors defined by clang (...D0Ev, 
...D1Ev, ...D2Ev)."

-- applied with minor tweaks. Thanks!

llvm-svn: 110194