ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.

llvm-svn: 69952

llvm-svn: 69934

Banksel immediate constant will always immediately follow the GA/ES, so scan an insn from beginnin to find out the banksel operand.

llvm-svn: 69883

memory operand tuples. This doesn't ever come up in normal
code however.

llvm-svn: 69848

Make the function begin label start after ther data pointer.
The address of data frame for function can be obtained by subtracting 2 from the function begin label.

llvm-svn: 69801

Spotted by gcc-4.5.

llvm-svn: 69673

This fixes PR4002.

llvm-svn: 69672

llvm-svn: 69665

This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.

llvm-svn: 69635

llvm-svn: 69624

in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock.  Thanks for Anton for suggesting this.

llvm-svn: 69615

llvm-svn: 69613

llvm-svn: 69605

llvm-svn: 69417

llvm-svn: 69394

llvm-svn: 69382

llvm-svn: 69381

punctuation.  No functional changes.

llvm-svn: 69378

for ARM.  Patch by Sandeep Patel.

llvm-svn: 69371

leaq	foo@TLSGD(%rip), %rdi

as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.

llvm-svn: 69350

llvm-svn: 69347

matter, because this instruction isn't generated until after
things that care.

llvm-svn: 69336

present, but it's inconsistent.

llvm-svn: 69335

this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts.  Thanks to Nicholas L for pointing this out.

llvm-svn: 69333

llvm-svn: 69284

llvm-svn: 69204

llvm-svn: 69203

llvm-svn: 69127

the local register allocator.

llvm-svn: 69115

either the source or destination is a physical h register.

This fixes sqlite3 with the post-RA scheduler enabled.

llvm-svn: 69111

REX prefixes.

llvm-svn: 69108

any non-address uses of the address value. This fixes 186.crafty.

llvm-svn: 69094

llvm-svn: 69049

llvm-svn: 69022

it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986

Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.

llvm-svn: 68964

 - Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.

llvm-svn: 68962

ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.

llvm-svn: 68959

llvm-svn: 68958

llvm-svn: 68954