Skip to content
  1. Dec 29, 2013
  2. Dec 28, 2013
    • Saleem Abdulrasool's avatar
      CodeGen: silence a C++11 feature warning · 7230b377
      Saleem Abdulrasool authored
      llvm-svn: 198133
      7230b377
    • Saleem Abdulrasool's avatar
      ARM IAS: handle errors more appropriately · 0c4b1026
      Saleem Abdulrasool authored
      Directive parsers must return false if the target assembler is interested in
      handling the directive.  The Error member function returns true always.  Using
      the 'return Error()' pattern would incorrectly indicate to the general parser
      that the target was not interested in the directive, when in reality it simply
      encountered a badly formed directive or some other error.  This corrects the
      behaviour to ensure that the parser behaves appropriately.
      
      llvm-svn: 198132
      0c4b1026
    • Andrew Trick's avatar
      Uninitialized variable (in never taken path) after factoring. · 7afe4818
      Andrew Trick authored
      llvm-svn: 198131
      7afe4818
    • Alp Toker's avatar
      Briefly document diag-build.sh · 8214bf5e
      Alp Toker authored
      It may be a quick and dirty script but it's still useful to have some
      indication as to its purpose.
      
      Text taken straight from Jordan's r158682 commit message.
      
      llvm-svn: 198128
      8214bf5e
    • Alp Toker's avatar
      Rename isBuiltinCall() to getBuiltinCallee() · a724cff0
      Alp Toker authored
      This better describes what the function does.
      
      Cleanup only.
      
      llvm-svn: 198127
      a724cff0
    • Alp Toker's avatar
      Tidy up CGCXXABI creation · 82862258
      Alp Toker authored
      'create' functions conventionally return a pointer, not a reference.
      
      Also use an OwningPtr to get replace the delete of a reference member.
      
      No functional change.
      
      llvm-svn: 198126
      82862258
    • Andrew Trick's avatar
      New machine model for cortex-a9. Schedule for resources and latency. · 3ca67d64
      Andrew Trick authored
      Schedule more conservatively to account for stalls on floating point
      resources and latency. Use the AGU resource to model latency stalls
      since it's shared between FP and LD/ST instructions. This might not be
      completely accurate but should work well in practice.
      
      llvm-svn: 198125
      3ca67d64
    • Andrew Trick's avatar
      Added debugging options: -misched-only-func/block · 33e05d76
      Andrew Trick authored
      llvm-svn: 198124
      33e05d76
    • Andrew Trick's avatar
      The Cortex-A9 machine model is incomplete. Mark it as such. · 03b22e39
      Andrew Trick authored
      Many vector operations never had itineraries. Since the new machine
      model was a mapping from existing itinerary classes, we don't have a
      model for these. We still want to migrate A9 even though no one has
      invested in a complete model, so mark it incomplete to avoid the
      scheduler asserting.
      
      llvm-svn: 198123
      03b22e39
    • Andrew Trick's avatar
      Add a PostMachineScheduler pass with generic implementation. · d14d7c20
      Andrew Trick authored
      PostGenericScheduler uses either the new machine model or the hazard
      checker for top-down scheduling. Most of the infrastructure for PreRA
      machine scheduling is reused.
      
      With a some tuning, this should allow MachineScheduler to be default
      for all ARM targets, including cortex-A9, using the new machine
      model. Likewise, with additional tuning, it should be able to replace
      PostRAScheduler for all targets.
      
      The PostMachineScheduler pass does not currently run the
      AntiDepBreaker. There is less need for it on targets that are already
      running preRA MachineScheduler. I want to prove it's necessary before
      committing to the maintenance burden.
      
      The PostMachineScheduler also currently removes kill flags and adds
      them all back later. This is a bit ridiculous. I'd prefer passes to
      directly use a liveness utility than rely on flags.
      
      A test case that enables this scheduler will be included in a
      subsequent checkin that updates the A9 model.
      
      llvm-svn: 198122
      d14d7c20
    • Andrew Trick's avatar
      Move the PostRA scheduler's fixupKills function for reuse. · 6b104f8b
      Andrew Trick authored
      llvm-svn: 198121
      6b104f8b
    • Andrew Trick's avatar
      Stub out a PostMachineScheduler pass. · 17080b9b
      Andrew Trick authored
      Placeholder and boilerplate for a PostRA MachineScheduler pass.
      
      llvm-svn: 198120
      17080b9b
Loading