registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

llvm-svn: 135183

llvm-svn: 135182

when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

llvm-svn: 135180

Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.

llvm-svn: 135179

of named struct types.

llvm-svn: 135178

llvm-svn: 135174

of calling getAllMetadata().  This is semantically identical, but doing
it this way avoids unpacking the DebugLoc.

llvm-svn: 135173

an MDNode.  This saves a bunch of time and memory in the IR linker, e.g. when 
doing LTO of files with debug info.

llvm-svn: 135172

llvm-svn: 135171

llvm-svn: 135169

ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168

const char* doesn't make sense.  Have it return StringRef instead.

llvm-svn: 135167

conceptually have nuls in it.

llvm-svn: 135165

llvm-svn: 135164

non-virtual function.

llvm-svn: 135163

llvm-svn: 135158

llvm-svn: 135157

The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156

llvm-svn: 135154

llvm-svn: 135151

instructions.

llvm-svn: 135146

Simplify some functions in the C API by using an ArrayRef to directly reference the array passed to them instead of copying it to a std::vector.

llvm-svn: 135145

[VECTOR-SELECT]
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.

llvm-svn: 135144

llvm-svn: 135143

llvm-svn: 135142

Part of rdar://9761830

llvm-svn: 135133

llvm-svn: 135132

TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.

This patch is but one small step towards fixing this. 500 more steps to go. :-(

llvm-svn: 135131

Original commit message:

Count references to interference cache entries.

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135130

llvm-svn: 135127

Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.

llvm-svn: 135126

llvm-svn: 135124

Fixes rdar://9761830

llvm-svn: 135123

llvm-svn: 135122

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135121

Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate.

llvm-svn: 135120

llvm-svn: 135119

llvm-svn: 135118

llvm-svn: 135117