- Nov 14, 2013
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Matt Arsenault authored
with the older version of the moveToVALU changes. llvm-svn: 194682
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Andrew Trick authored
If a null call target is provided, don't emit a dummy call. This allows the runtime to reserve as little nop space as it needs without the requirement of emitting a call. llvm-svn: 194676
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Kevin Qin authored
llvm-svn: 194673
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Rafael Espindola authored
There is nothing special about quotes and newlines from the object file point of view, only the assembler has to worry about expanding the \n and \". This patch then removes the special handling from the Mangler. llvm-svn: 194667
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Kevin Qin authored
llvm-svn: 194656
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Jiangning Liu authored
llvm-svn: 194648
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Reed Kotler authored
constant islands. llvm-svn: 194630
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Tom Stellard authored
Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
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Tom Stellard authored
All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
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- Nov 13, 2013
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Chad Rosier authored
instructions. This patch does not include the shift right and accumulate instructions. A number of non-overloaded intrinsics have been remove in favor of their overloaded counterparts. llvm-svn: 194598
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Weiming Zhao authored
By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. llvm-svn: 194592
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Rafael Espindola authored
Accepting quotes is a property of an assembler, not of an object file. For example, ELF can support any names for sections and symbols, but the gnu assembler only accepts quotes in some contexts and llvm-mc in a few more. LLVM should not produce different symbols based on a guess about which assembler will be reading the code it is printing. llvm-svn: 194575
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Robert Lytton authored
llvm-svn: 194564
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Reed Kotler authored
specifically about the .space directive. This allows us to force large blocks of code to appear in test cases for things like constant islands without having to make giant test cases to force things like long branches to take effect. llvm-svn: 194555
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Andrew Trick authored
llvm-svn: 194553
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Matt Arsenault authored
llvm-svn: 194547
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Juergen Ributzka authored
This patch reapplies r193676 with an additional fix for the Hexagon backend. The SystemZ backend has already been fixed by r194148. The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask type for the given target. Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. Reviewed by Nadav llvm-svn: 194542
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- Nov 12, 2013
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Andrew Trick authored
I still don't know how to refer to the fixed operands symbolically. I plan to look into it. llvm-svn: 194529
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Akira Hatanaka authored
argument was not being passed in $f14. llvm-svn: 194522
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Akira Hatanaka authored
llvm-svn: 194519
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Akira Hatanaka authored
llvm-svn: 194510
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Andrew Trick authored
We already know how to fold a reload from a frameindex without analyzing the load instruction. Generalize this to handle any frameindex load. This streamlines the logic for rematerializing loads from stack arguments. As a side effect, it allows stackmaps to record a stack argument location without spilling it. Verified no effect on codegen for llvm test-suite. llvm-svn: 194497
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Daniel Sanders authored
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
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Daniel Sanders authored
llvm-svn: 194471
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Bradley Smith authored
llvm-svn: 194470
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Daniel Sanders authored
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
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Daniel Sanders authored
[mips][msa] Change constant used in ori tests to avoid conflict with bseti (also xori to avoid bnegi) Upcoming commit(s) are going to add support for bseti and bnegi. This would cause some existing tests to (correctly) change behaviour and emit a different instruction. This patch prevents this by changing the constant used in ori and xori tests so that they will not be matchable by the bseti and bnegi patterns when these instructions are matchable from normal IR. llvm-svn: 194467
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Robert Lytton authored
llvm-svn: 194466
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Robert Lytton authored
llvm-svn: 194465
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Robert Lytton authored
ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There is no need to emit an instructions since the XCore provides sequential consistency. Original patch by Richard Osborne llvm-svn: 194464
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Robert Lytton authored
llvm-svn: 194463
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Matt Arsenault authored
Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
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Reed Kotler authored
This has no material effect at this time since we don't have a direct object emitter for mips16 and the assembler can't tell them apart. I place a comment "16 bit inst" for those so that I can tell them apart in the output. The constant island pass has only been minimally changed to allow this. More complete branch work is forthcoming but this is the first step. llvm-svn: 194442
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Matt Arsenault authored
llvm-svn: 194433
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- Nov 11, 2013
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Andrew Trick authored
Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!" The primary purpose of anyregcc is to prevent a patchpoint's call arguments and return value from being spilled. They must be available in a register, although the calling convention does not pin the register. It's up to the front end to avoid using this convention for calls with more arguments than allocatable registers. llvm-svn: 194428
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Vincent Lejeune authored
llvm-svn: 194425
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Akira Hatanaka authored
the floating point register mode. llvm-svn: 194423
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Justin Holewinski authored
llvm-svn: 194410
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Justin Holewinski authored
llvm-svn: 194409
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Chad Rosier authored
source operands, a vector, an element to insert, and a shift amount. llvm-svn: 194406
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