llvm-svn: 24721

llvm-svn: 24720

from the DAGToDAG cpp file.  This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.

Allows us to match:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  %tmp3 = add <4 x float> %tmp2, %tmp1
  store <4 x float> %tmp3, <4 x float> *%a
  ret void
}

As:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vmaddfp v0, v0, v0, v0
        stvx v0, r2, r3
        blr

Or, with llc -disable-excess-fp-precision,

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v1, v0, v0, v1
        vaddfp v0, v1, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24719

llvm-svn: 24717

llvm-svn: 24716

llvm-svn: 24715

OtherVT, it cannot be compare to type of 1st operand which is an integer type.

llvm-svn: 24713

llvm-svn: 24705

llvm-svn: 24703

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

Is selected to:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v0, v0, v0, v1
        stvx v0, r2, r3
        blr

llvm-svn: 24701

llvm-svn: 24700

llvm-svn: 24696

llvm-svn: 24695

llvm-svn: 24693

llvm-svn: 24692

llvm-svn: 24690

llvm-svn: 24689

A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.

llvm-svn: 24688

llvm-svn: 24687

llvm-svn: 24686

llvm-svn: 24685

llvm-svn: 24684

llvm-svn: 24683

  This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682

llvm-svn: 24681

llvm-svn: 24675

base or index operands being selected.

llvm-svn: 24674

first before the chain.
e.g.
int X;

int foo(int x)
{
  x += X + 37;
  return x;
}

If chain operand is selected first, we would generate:
	movl X, %eax
	movl 4(%esp), %ecx
	leal 37(%ecx,%eax), %eax

rather than
	movl $37, %eax
	addl 4(%esp), %eax
	addl X, %eax

which does not require %ecx. (Due to ADD32rm not matching.)

llvm-svn: 24673

llvm-svn: 24672

llvm-svn: 24671

llvm-svn: 24670

llvm-svn: 24668

llvm-svn: 24664

llvm-svn: 24662

llvm-svn: 24661

llvm-svn: 24660

llvm-svn: 24659

FP select improvements (and likely breakage), oh and crazy people might want to *return* floating point values.  Don't see why myself

llvm-svn: 24658

them in the PPC backend, to simplify some logic out of Select and
SelectAddr.

llvm-svn: 24657

llvm-svn: 24656