mechanism. To support this, make MachineFunctionPass a little more
complete.

llvm-svn: 77654

llvm-svn: 77649

llvm-svn: 77640

llvm-svn: 77635

Start using DebugInfoFinder.

llvm-svn: 77621

Allow targets to define libcall names for mem(cpy,set,move) intrinsics, rather than hardcoding them in DAG lowering.

llvm-svn: 77586

Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 

When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582

llvm-svn: 77516

now that TargetOperandInfo does the heavy lifting.

llvm-svn: 77508

llvm-svn: 77505

   and convert code to using it, instead of having lots of things
   poke the isLookupPtrRegClass() method directly.

2. Make PointerLikeRegClass contain a 'kind' int, and store it in
   the existing regclass field of TargetOperandInfo when the
   isLookupPtrRegClass() predicate is set.  Make getRegClass pass
   this into TargetRegisterInfo::getPointerRegClass(), allowing
   targets to have multiple ptr_rc things.

llvm-svn: 77504

llvm-svn: 77495

llvm-svn: 77494

No functionality change.

llvm-svn: 77432

llvm-svn: 77412

  correct. But what are you going to do? I'll fix this in the future.
- Move another large loop into its own method.

llvm-svn: 77408

Does any one else hate the name "const_reverse_iterator" as much as I do?

llvm-svn: 77399

llvm-svn: 77394

llvm-svn: 77393

going to emit.

llvm-svn: 77382

llvm-svn: 77373

llvm-svn: 77369

llvm-svn: 77366

llvm-svn: 77354

llvm-svn: 77347

Add reload and remat backscheduling.  This is disabled by default.  Use
-schedule-spills=true to enable.

llvm-svn: 77327

it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.

Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.

This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
   pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
   CStringSection_.  Factor the code better.
5. fixes some bugs in string lowering on ELF targets.

llvm-svn: 77294

llvm-svn: 77271

llvm-svn: 77266

MCSections soon instead of Section for all targets, and we need something to
own them.

llvm-svn: 77252

llvm-svn: 77247

llvm-svn: 77239

llvm-svn: 77238

llvm-svn: 77232

instead and drive things based off of that.

llvm-svn: 77184

change.

llvm-svn: 77171

llvm-svn: 77152

llvm-svn: 77148

just use a smallstring instead.

llvm-svn: 77144

to its classification.

llvm-svn: 77140