index for the input pattern in terms of the output pattern. Instead
keep track of how many fixed operands the input pattern actually
has, and have the input matching code pass the output-emitting
function that index value. This simplifies the code, disentangles
variables_ops from the support for predication operations, and
makes variable_ops more robust.

llvm-svn: 51808

llvm-svn: 51792

llvm-svn: 51761

cases due to an isel deficiency already noted in
lib/Target/X86/README.txt, but they can be matched in this fold-call.ll
testcase, for example.

This is interesting mainly because it exposes a tricky tblgen bug;
tblgen was incorrectly computing the starting index for variable_ops
in the case of a complex pattern.

llvm-svn: 51706

function to flush a specified std::ostream.

llvm-svn: 51705

definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.

This fixes "rdar://5791600", whatever that is ;-).

llvm-svn: 51699

memmove to a more plausible value, now that it's actually being used.

llvm-svn: 51696

llvm-svn: 51667

llvm-svn: 51664

like.

llvm-svn: 51662

instruction to execute. This can be used for transformations (like two-address
conversion) to remat an instruction instead of generating a "move"
instruction. The idea is to decrease the live ranges and register pressure and
all that jazz.

llvm-svn: 51660

llvm-svn: 51644

llvm-svn: 51635

llvm-svn: 51634

on ia64.

llvm-svn: 51633

llvm-svn: 51632

llvm-svn: 51631

llvm-svn: 51630

is a memory location

llvm-svn: 51626

code generator would do something like this:

f64 = load f32 <anyext>, f32mem
v2f64 = insertelt undef, %0, 0
v2f64 = insertelt %1, 0.0, 1

into 

v2f64 = vzext_load f32mem

which on x86 is movsd, when you really wanted a cvtss2sd/movsd pair.

llvm-svn: 51624

llvm-svn: 51591

llvm-svn: 51538

llvm-svn: 51533

Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles.

llvm-svn: 51531

so that gcc doesn't warn about them.

llvm-svn: 51529

sections on ppc32 darwin.  g++.dg/abi/key2.C

llvm-svn: 51527

llvm-svn: 51526

Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into load and shuffle instructions.

llvm-svn: 51522

llvm-svn: 51503

llvm-svn: 51501

llvm-svn: 51491

llvm-svn: 51490

load-folding table entries for PMULDQ and PMULLD.

llvm-svn: 51489

llvm-svn: 51487

This fixes recent CBE regressions.

llvm-svn: 51483

instruction for doing this?

llvm-svn: 51473

Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks.
Also fixed some 80 col. violations.

llvm-svn: 51462

g++.dg/abi/key2.C

llvm-svn: 51458

X86CodeEmitter should not set PIC style to None at initialization time. This will break codegen if relocation model is changed to PIC_ later.

llvm-svn: 51455

llvm-svn: 51435