No functional change intended.

llvm-svn: 140664

I'll clean up the source in the next commit.

llvm-svn: 140663

llvm-svn: 140661

This also enables domain swizzling for AVX code which required a few
trivial test changes.

The pass will be moved to lib/CodeGen shortly.

llvm-svn: 140659

llvm-svn: 140655

llvm-svn: 140653

I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass.  They are essentially doing the same
thing.

llvm-svn: 140652

Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647

current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.

llvm-svn: 140646

of the instruction definitions using Pat<>.

llvm-svn: 140644

a suboptimal schedule.

llvm-svn: 140643

test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.

llvm-svn: 140641

Naming conventions consistency. No functional change.

llvm-svn: 140636

Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.

If someone prefers %tmp42 to %42, run instnamer.

llvm-svn: 140634

llvm-svn: 140631

require special case handling.
rdar://10117377

llvm-svn: 140629

llvm-svn: 140627

llvm-svn: 140626

llvm-svn: 140625

llvm-svn: 140624

llvm-svn: 140622

llvm-svn: 140619

a couple of outstanding issues with frame objects occuring as instruction
operands.

llvm-svn: 140616

llvm-svn: 140615

Return numbers of 64-bit registers.

llvm-svn: 140609

llvm-svn: 140607

llvm-svn: 140606

Add a new method: getAnyExtOrTrunc and use it to replace the manual check.

llvm-svn: 140603

while the decision is to bit-pack small values.

llvm-svn: 140601

llvm-svn: 140600

llvm-svn: 140598

llvm-svn: 140593

split landingpad instructions into a PHI node.
PR11016

llvm-svn: 140592

Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.

llvm-svn: 140590

llvm-svn: 140585

llvm-svn: 140583

llvm-svn: 140582

llvm-svn: 140581

The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.

llvm-svn: 140580

llvm-svn: 140579