Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.

llvm-svn: 134569

llvm-svn: 134568

llvm-svn: 134566

When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors.  They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF).

Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.

<rdar://problem/9716278>

llvm-svn: 134565

llvm-svn: 134563

llvm-svn: 134561

llvm-svn: 134559

llvm-svn: 134557

llvm-svn: 134555

  vec.insert(vec.begin(), vec[3]);
The issue was that vec[3] returns a reference into the vector, which is invalidated when insert() memmove's the elements down to make space.  The method needs to specifically detect and handle this case to correctly match std::vector's semantics.

Thanks to Howard Hinnant for clarifying the correct behavior, and explaining how std::vector solves this problem.

llvm-svn: 134554

llvm-svn: 134549

llvm-svn: 134547

llvm-svn: 134546

llvm-svn: 134545

This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540

For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.

llvm-svn: 134539

llvm-svn: 134538

careful about referencing values.

llvm-svn: 134537

Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533

llvm-svn: 134532

llvm-svn: 134530

llvm-svn: 134528

llvm-svn: 134527

llvm-svn: 134525

llvm-svn: 134521

The promotion code lost any alignment information, when hoisting loads and
stores out of the loop. This lead to incorrect aligned memory accesses. We now
use the largest alignment we can prove to be correct.

llvm-svn: 134520

llvm-svn: 134517

llvm-svn: 134516

llvm-svn: 134511

push with a small constant produces a 2-byte push.

llvm-svn: 134501

llvm-svn: 134498

llvm-svn: 134457

llvm-svn: 134447

extension points to be used by clang.

llvm-svn: 134444

llvm-svn: 134441

llvm-svn: 134440

llvm-svn: 134439

llvm-svn: 134436

llvm-svn: 134433

llvm-svn: 134431