Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

llvm-svn: 104293

allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854

Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481

was unused. TargetMachine::getSubtarget() is used instead.

llvm-svn: 103474

changes before doing phi lowering for switches.

llvm-svn: 102809

const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635

MachineFunctionInfo subclasses.

llvm-svn: 101634

Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100304

llvm-svn: 100199

Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100191

llvm-svn: 99948

e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.

llvm-svn: 99928

--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010

llvm-svn: 98889

llvm-svn: 98888

llvm-svn: 98502

Radar 7461718.

llvm-svn: 96572

llvm-svn: 95603

llvm-svn: 95160

llvm-svn: 95130

Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.

llvm-svn: 94626

"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758

just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200

llvm-svn: 91090

Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.

llvm-svn: 91003

llvm-svn: 86964

Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.

llvm-svn: 86858

llvm-svn: 86494

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

llvm-svn: 85362

This fixes PR5031. Unfortunately, there is no small testcase :(

llvm-svn: 82643

Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273

llvm-svn: 80773

The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117

now using shuffles instead of intrinsics.

llvm-svn: 79673

llvm-svn: 79625

llvm-svn: 79624

Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle

llvm-svn: 79619

This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428