llvm-svn: 54374

looks bogus. Please see PR2629 for details on why this is breaking things.

llvm-svn: 54372

llvm-svn: 54371

llvm-svn: 54369

llvm-svn: 54362

llvm-svn: 54361

llvm-svn: 54360

that couldn't be updated.

llvm-svn: 54359

llvm-svn: 54358

llvm-svn: 54357

llvm-svn: 54356

llvm-svn: 54355

llvm-svn: 54354

llvm-svn: 54351

llvm-svn: 54350

llvm-svn: 54349

llvm-svn: 54348

llvm-svn: 54347

Fix PR2568: Fix bug that cause redudant kill marker after its live interval has been extended due to coalescing.

llvm-svn: 54346

llvm-svn: 54337

llvm-svn: 54336

Update these tests to work by disabling the new correct CFG generation.  This flag should ONLY be used to for tests like these.

llvm-svn: 54334

- Add a basic machine-level dead block eliminator.

These two have to go together, since many other parts of the code generator are unable to handle the unreachable blocks otherwise created.

llvm-svn: 54333

version uses a new algorithm for evaluating the binomial coefficients 
which is significantly more efficient for AddRecs of more than 2 terms 
(see the comments in the code for details on how the algorithm works).  
It also fixes some bugs: it removes the arbitrary length restriction for 
AddRecs, it fixes the silent generation of incorrect code for AddRecs 
which require a wide calculation width, and it fixes an issue where we 
were incorrectly truncating the iteration count too far when evaluating 
an AddRec expression narrower than the induction variable.

There are still a few related issues I know of: I think there's 
still an issue with the SCEVExpander expansion of AddRec in terms of
the width of the induction variable used.  The hack to avoid generating 
too-wide integers shouldn't be necessary; instead, the callers should be 
considering the cost of the expansion before expanding it (in addition 
to not expanding too-wide integers, we might not want to expand 
expressions that are really expensive, especially when optimizing for 
size; calculating an length-17 32-bit AddRec currently generates about 250 
instructions of straight-line code on X86).  Also, for long 32-bit 
AddRecs on X86, CodeGen really sucks at scheduling the code.  I'm planning on 
filing follow-up PRs for these issues.

llvm-svn: 54332

This allows it to work correctly on aggregate values.
This fixes PR2623.

llvm-svn: 54331

This allows it to work correctly on nested aggregate values.
This fixes PR2625.

llvm-svn: 54330

llvm-svn: 54329

aren't used anyway, they also used to broke compiling when fastcc was specified for a
function, but not anymore.

llvm-svn: 54316

llvm-svn: 54315

llvm-svn: 54314

llvm-svn: 54313

llvm-svn: 54312

Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug

llvm-svn: 54274

llvm-svn: 54273

llvm-svn: 54266

llvm-svn: 54262

llvm-svn: 54251

llvm-svn: 54250

the default legalizer.

llvm-svn: 54249

switches use the binary search algorithm) for
environments that don't support it.  PPC64 JIT
is such an environment; turn the flag on for that.

llvm-svn: 54248