llvm-svn: 121805

llvm-svn: 121801

registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

llvm-svn: 121800

llvm-svn: 121798

llvm-svn: 121797

is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794

regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995

llvm-svn: 121793

llvm-svn: 121792

warning in the opt build.

llvm-svn: 121791

llvm-svn: 121790

llvm-svn: 121789

llvm-svn: 121788

llvm-svn: 121784

llvm-svn: 121783

LiveIntervalUnions.

llvm-svn: 121781

llvm-svn: 121780

set for interworking to work properly. rdar://8755956

llvm-svn: 121778

llvm-svn: 121774

llvm-svn: 121772

llvm-svn: 121769

llvm-svn: 121765

   which is simpler than finding a place to insert in BB.
 - Don't perform the 'if condition hoisting' xform on certain
   i1 PHIs, as it interferes with switch formation.

This re-fixes "example 7", without breaking the world hopefully.

llvm-svn: 121764

first, it can kick in on blocks whose conditions have been
folded to a constant, even though one of the edges will be
trivially folded.

second, it doesn't clean up the "if diamond" that it just 
eliminated away.  This is a problem because other simplifycfg
xforms kick in depending on the order of block visitation,
causing pointless work.

llvm-svn: 121762

breaking the selfhost builds, though I can't fathom how.

llvm-svn: 121761

when all 2-entry phis are simplified away.

llvm-svn: 121760

don't print it unless the xform happens.

llvm-svn: 121758

llvm-svn: 121757

llvm-svn: 121756

llvm-svn: 121755

GetIfCondition faster by avoiding pred_iterator.  No
really interesting change.

llvm-svn: 121754

llvm-svn: 121753

code a bit, switch from constant folding to instsimplify.

llvm-svn: 121751

llvm-svn: 121750

work, but fixes 400.perlbmk.

llvm-svn: 121749

instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747

llvm-svn: 121746

llvm-svn: 121743

llvm-svn: 121741

llvm-svn: 121740

llvm-svn: 121738