llvm-svn: 50475

llvm-svn: 50473

to instcombine.

llvm-svn: 50472

llvm-svn: 50465

llvm-svn: 50464

llvm-svn: 50463

fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().

llvm-svn: 50462

DAG.UpdateNodeOperands() is called before (not after) the call to
TLI.LowerOperation().

llvm-svn: 50461

targets.

llvm-svn: 50451

Revert r50441.  The original code was correct.  Add some more comments so that I don't make the same mistake in the future.

llvm-svn: 50446

we were checking for it in the wrong order.  This caused a miscompilation because the
return slot optimization assumes that the call it is dealing with is NOT a memcpy.

llvm-svn: 50444

llvm-svn: 50442

of this was suggested by Chris.

llvm-svn: 50441

llvm-svn: 50437

llvm-svn: 50436

llvm-svn: 50433

This fixes the second half of PR2262

llvm-svn: 50430

llvm-svn: 50428

This removes the existing bottleneck related to the removal of elements from 
the middle of the queue.

Also fixes a subtle bug in ScheduleDAGRRList::CapturePred:
It was updating the state of the SUnit before removing it. As a result, the
comparison operators were working incorrectly and this SUnit could not be removed 
from the queue properly.

Reviewed by Evan and Dan. Approved by Dan.

llvm-svn: 50412

generalizes the previous code to handle the case when the string is not
an immediate to the strlen call (for example, crazy stuff like 
strlen(c ? "foo" : "bart"+1) -> 3).  This implements 
gcc.c-torture/execute/builtins/strlen-2.c.  I will generalize other
cases in simplifylibcalls to use the same routine later.

llvm-svn: 50408

llvm-svn: 50406

llvm-svn: 50390

We now compile test2/test3 to:

_test2:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	addps	%xmm1, %xmm0
	ret
_test3:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	paddd	%xmm1, %xmm0
	ret

as expected.

llvm-svn: 50389

towards PR2094.  It now compiles the attached .ll file to:

_sad16_sse2:
	movslq	%ecx, %rax
	## InlineAsm Start
	%ecx %rdx %rax %rax %r8d %rdx %rsi
	## InlineAsm End
	## InlineAsm Start
	set %eax
	## InlineAsm End
	ret

which is pretty decent for a 3 output, 4 input asm.

llvm-svn: 50386

e.g.
vr1024<2> extract_subreg vr1025, 2
If vr1024 do not have the same register class as vr1025, it's not safe to coalesce this away. For example, vr1024 might be a GPR32 while vr1025 might be a GPR64.

llvm-svn: 50385

llvm-svn: 50384

llvm-svn: 50383

the trip count.

llvm-svn: 50382

Fix a bug in RegsForValue::getCopyToRegs() that causes cyclical scheduling units. If it's creating multiple CopyToReg nodes that are "flagged" together, it should not create a TokenFactor for it's chain outputs:

c1, f1 = CopyToReg                                                                                                                                                                                             
c2, f2 = CopyToReg                                                                                                                                                                                             
c3     = TokenFactor c1, c2                                                                                                                                                                                    
 ...                                                                                                                                                                                                                      
       = user c3, ..., f2

Now that the two CopyToReg's and the user are "flagged" together. They effectively forms a single scheduling unit. The TokenFactor is now both an operand and a successor of the Flagged nodes.

llvm-svn: 50376

be truncated to 32 bits. This fixes the recent Benchmarks/McCat/09-vor
regression on x86-64, among other things.

llvm-svn: 50372

llvm-svn: 50370

if the zext is not legal.

llvm-svn: 50368

llvm-svn: 50367

aggregate types.

llvm-svn: 50366

reorder some of the members for clarity.

llvm-svn: 50365

Bug fix in BumpPtrAllocator: don't assume that all objects have the same alignment.  "Bump" of the pointer for the next allocated object to be of the specified alignment.

llvm-svn: 50362

llvm-svn: 50361

Patch by Anders Johnsen!

llvm-svn: 50360

memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.

llvm-svn: 50359

ComputeMaskedBits knows about cttz, ctlz, and ctpop. Teach
SelectionDAG's ComputeMaskedBits what InstCombine's knows
about SRem. And teach them both some things about high bits
in Mul, UDiv, URem, and Sub. This allows instcombine and
dagcombine to eliminate sign-extension operations in
several new cases.

llvm-svn: 50358