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  1. Mar 08, 2013
    • Jakob Stoklund Olesen's avatar
      Add a getPassName() method. · bed16542
      Jakob Stoklund Olesen authored
      llvm-svn: 176669
      bed16542
    • Jakob Stoklund Olesen's avatar
      Rename isEarlierInSameTrace to isUsefulDominator. · 299cedc7
      Jakob Stoklund Olesen authored
      In very rare cases caused by irreducible control flow, the dominating
      block can have the same trace head without actually being part of the
      trace.
      
      As long as such a dominator still has valid instruction depths, it is OK
      to use it for computing instruction depths.
      
      Rename the function to avoid lying, and add a check that instruction
      depths are computed for the dominator.
      
      llvm-svn: 176668
      299cedc7
  2. Mar 07, 2013
  3. Mar 05, 2013
  4. Mar 02, 2013
  5. Mar 01, 2013
    • Akira Hatanaka's avatar
      Set properties for f128 type. · 3d055580
      Akira Hatanaka authored
      llvm-svn: 176378
      3d055580
    • Chad Rosier's avatar
      Generate an error message instead of asserting or segfaulting when we can't · b3864609
      Chad Rosier authored
      handle indirect register inputs.
      rdar://13322011
      
      llvm-svn: 176367
      b3864609
    • Michael Liao's avatar
      Fix PR10475 · 6af16fc3
      Michael Liao authored
      - ISD::SHL/SRL/SRA must have either both scalar or both vector operands
        but TLI.getShiftAmountTy() so far only return scalar type. As a
        result, backend logic assuming that breaks.
      - Rename the original TLI.getShiftAmountTy() to
        TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
        return target-specificed scalar type or the same vector type as the
        1st operand.
      - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
        type.
      
      llvm-svn: 176364
      6af16fc3
    • Andrew Trick's avatar
      Scheduler diagnostics. Print the register name. · f9669bea
      Andrew Trick authored
      llvm-svn: 176316
      f9669bea
    • Andrew Trick's avatar
      Instructions schedulers should report correct height/depth. · 2a8edef7
      Andrew Trick authored
      We avoided computing DAG height/depth during Node printing because it
      shouldn't depend on an otherwise valid DAG. But this has become far
      too annoying for the common case of a valid DAG where we want to see
      valid values. If doing the computation on-the-fly turns out to be a
      problem in practice, then I'll add a mode to the diagnostics to only
      force it when we're likely to have a valid DAG, otherwise explicitly
      print INVALID instead of bogus numbers. For now, just go for it all
      the time.
      
      llvm-svn: 176314
      2a8edef7
    • Eli Bendersky's avatar
      A small refactoring + adding comments. · 33ebf836
      Eli Bendersky authored
      SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it
      makes sense to pass it the function instead of extracting a basic-block from
      the function and then tossing it. This is also more self-documenting (functions
      have arguments, BBs don't).
      
      In addition, added comments to a couple of Select* methods.
      
      llvm-svn: 176305
      33ebf836
  6. Feb 28, 2013
  7. Feb 27, 2013
  8. Feb 26, 2013
  9. Feb 25, 2013
    • Chad Rosier's avatar
      Fix wording. · 0587597f
      Chad Rosier authored
      llvm-svn: 176055
      0587597f
    • Chad Rosier's avatar
      [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 or · a92ef4ba
      Chad Rosier authored
      fewer scalar integer (i32 or i64) arguments. It completely eliminates the need
      for SDISel for trivial functions.
      
      Also, add the new llc -fast-isel-abort-args option, which is similar to
      -fast-isel-abort option, but for formal argument lowering.
      
      llvm-svn: 176052
      a92ef4ba
    • Andrew Trick's avatar
      pre-RA-sched fix: only reevaluate physreg interferences when necessary. · 7cf43619
      Andrew Trick authored
      Fixes rdar:13279013: scheduler was blowing up on select instructions.
      
      llvm-svn: 176037
      7cf43619
    • Matt Beaumont-Gay's avatar
      'Hexadecimal' has two 'a's and only one 'i'. · 0e760da5
      Matt Beaumont-Gay authored
      llvm-svn: 176031
      0e760da5
    • Chandler Carruth's avatar
      Fix spelling noticed by Duncan. · 121dbf88
      Chandler Carruth authored
      llvm-svn: 176023
      121dbf88
    • Chandler Carruth's avatar
      Fix the root cause of PR15348 by correctly handling alignment 0 on · 05920b18
      Chandler Carruth authored
      memory intrinsics in the SDAG builder.
      
      When alignment is zero, the lang ref says that *no* alignment
      assumptions can be made. This is the exact opposite of the internal API
      contracts of the DAG where alignment 0 indicates that the alignment can
      be made to be anything desired.
      
      There is another, more explicit alignment that is better suited for the
      role of "no alignment at all": an alignment of 1. Map the intrinsic
      alignment to this early so that we don't end up generating aligned DAGs.
      
      It is really terrifying that we've never seen this before, but we
      suddenly started generating a large number of alignment 0 memcpys due to
      the new code to do memcpy-based copying of POD class members. That patch
      contains a bug that rounds bitfield alignments down when they are the
      first field. This can in turn produce zero alignments.
      
      This fixes weird crashes I've seen in library users of LLVM on 32-bit
      hosts, etc.
      
      llvm-svn: 176022
      05920b18
  10. Feb 24, 2013
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