llvm-svn: 27763

llvm-svn: 27762

llvm-svn: 27761

This implements vec_constants.ll:test_vsldoi and test_rol

llvm-svn: 27760

llvm-svn: 27759

llvm-svn: 27758

llvm-svn: 27755

new patterns.

llvm-svn: 27754

llvm-svn: 27753

PowerPC/vec_constants.ll:test_29.

llvm-svn: 27752

llvm-svn: 27751

Effeciently codegen even splats in the range [-32,30].

This allows us to codegen <30,30,30,30> as:

        vspltisw v0, 15
        vadduwm v2, v0, v0

instead of as a cp load.

llvm-svn: 27750

llvm-svn: 27749

if it can be implemented in 3 or fewer discrete altivec instructions, codegen
it as such.  This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll

llvm-svn: 27748

and shouldn't be lowered to vperm.

llvm-svn: 27747

llvm-svn: 27746

llvm-svn: 27745

llvm-svn: 27744

llvm-svn: 27743

llvm-svn: 27742

llvm-svn: 27741

llvm-svn: 27740

of various 4-element vectors.

llvm-svn: 27739

llvm-svn: 27738

llvm-svn: 27737

Altivec vectors.

llvm-svn: 27736

llvm-svn: 27735

llvm-svn: 27734

llvm-svn: 27733

address has to be 16-byte aligned but the values aren't spilled to 128-bit
locations.

llvm-svn: 27732

one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.

llvm-svn: 27731

to write one pattern for vector stores instead of 4.

llvm-svn: 27730

Remove some done items from the todo list.

llvm-svn: 27729

Make the insert/extract elt -> shuffle code more aggressive.

This fixes CodeGen/PowerPC/vec_shuffle.ll

llvm-svn: 27728

llvm-svn: 27727

llvm-svn: 27726

go away when I start using evan's binop type canonicalizer

llvm-svn: 27725

bitconverted from some other type.

llvm-svn: 27724

buildvectors.

llvm-svn: 27723

llvm-svn: 27722