Fix a leak that this turned up in LowerSubregs.cpp.
And, comment a leak in LiveIntervalAnalysis.cpp.

llvm-svn: 53746

llvm-svn: 53504

Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503

- Change the horrible N^2 isRegReDefinedByTwoAddr. Now callers must supply the operand index of def machineoperand and at most one full scan of non-implicit operands is needed.
- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.

llvm-svn: 53394

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097

Remember which MachineOperand we were processing, so we don't have to scan the list to find it again later.
This speeds up live intervals from 0.37s to 0.30s on instcombine.

llvm-svn: 52745

llvm-svn: 52572

llvm-svn: 52485

llvm-svn: 52477

add new instructions.

llvm-svn: 52475

llvm-svn: 52431

llvm-svn: 52345

impact on code quality or compile time.

llvm-svn: 52329

llvm-svn: 52306

Assign indices to empty basic blocks.  This will be necessary for StrongPHIElimination in the near future.

llvm-svn: 52300

llvm-svn: 52040

llvm-svn: 52012

llvm-svn: 51934

llvm-svn: 51876

Make the renumbering correct in the face of deleted instructions that have been removed from the LiveIntervals maps.

llvm-svn: 51714

llvm-svn: 51704

llvm-svn: 51694

Renumbering needs to account for instruction slot offsets when performing lookups in the index maps.

llvm-svn: 51691

llvm-svn: 51658

Factor the numbering computation into a separate method, and add the slightest attempt at some renumbering logic, which is currently unused.

llvm-svn: 51652

llvm-svn: 51513

When rewriting defs and uses after spilling, don't set the weight of a
live interval to infinity if the instruction being rewritten is an
original remat def instruction.  We were only checking against the clone
of the remat def which doesn't actually appear in the IR at all.

llvm-svn: 51440

llvm-svn: 51305

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

llvm-svn: 50696

llvm-svn: 49800

Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled.

llvm-svn: 49542

- Added insert_subreg coalescing support.

llvm-svn: 49448

- Eliminate an implicit_def when it's being spilled.

llvm-svn: 49166

llvm-svn: 49053

llvm-svn: 49002

The support for remat of instructions with a register operand is hackish, to say the least. Since the register operand guaranteed to be PIC base and that it is already live at all uses, we are making sure it will not be spilled after its uses are rematerialized for both performance and correctness reasons.

llvm-svn: 48976

llvm-svn: 48381

llvm-svn: 48246