take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.

llvm-svn: 113570

llvm-svn: 113566

more clear.  No functional change.

llvm-svn: 113565

bad as I'd thought.

llvm-svn: 113561

some data around and implement a couple of move routines to do this.

llvm-svn: 113546

llvm-svn: 113537

Truncate when truncating, extend when extending.

llvm-svn: 113536

llvm-svn: 113533

llvm-svn: 113523

llvm-svn: 113522

instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513

llvm-svn: 113508

llvm-svn: 113501

llvm-svn: 113478

the VST pseudos.  The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.

llvm-svn: 113473

llvm-svn: 113463

uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX.  No (intended) functional change.

llvm-svn: 113462

llvm-svn: 113461

llvm-svn: 113459

operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

llvm-svn: 113456

llvm-svn: 113455

for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.

llvm-svn: 113453

For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.

llvm-svn: 113452

llvm-svn: 113442

llvm-svn: 113440

llvm-svn: 113436

llvm-svn: 113435

llvm-svn: 113427

llvm-svn: 113426

llvm-svn: 113422

llvm-svn: 113420

llvm-svn: 113417

llvm-svn: 113409

llvm-svn: 113406

Re-running some nightly testers w/ it enabled to verify.

llvm-svn: 113399

pointer was intended. rdar://8401980

llvm-svn: 113394

Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.

llvm-svn: 113388

llvm-svn: 113387

llvm-svn: 113378

nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.

llvm-svn: 113369