Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.

This fixes PR10221.

llvm-svn: 134776

llvm-svn: 134775

llvm-svn: 134774

Really force on 64bit for 64-bit targets.  Should fix remaining failures on unknown x86/non-x86 targets.

llvm-svn: 134773

llvm-svn: 134772

llvm-svn: 134771

Note that because we don't usually touch the MMX registers anyway, all -mno-mmx needs to do is tweak the x86-32 calling convention a little for vectors that look like MMX vectors, and prevent the definition of __MMX__.

clang doesn't actually stop the user from using MMX inline asm operands or MMX builtins in -mno-mmx mode; as a QOI issue, it would be nice to diagnose, but I doubt it really matters much.

<rdar://problem/9694837>

llvm-svn: 134770

llvm-svn: 134769

Revert earlier unnecessary hack.  Make sure we correctly force on 64bit and cmov for 64-bit targets.

llvm-svn: 134768

Add a usage example of SBEvent APIs.

o SBEvent.h and SBListener.h:

Add method docstrings for SBEvent.h and SBListener.h, and example usage of SBEvent into
the class docstring of SBEvent.

o lldb.swig:

Add typemap for SBEvent::SBEvent (uint32_t event, const char *cstr, uint32_t cstr_len)
so that we can use, in Python, obj2 = lldb.SBEvent(0, "abc") to create an SBEvent.

llvm-svn: 134766

llvm-svn: 134765

llvm-svn: 134764

llvm-svn: 134763

llvm-svn: 134762

llvm-svn: 134761

llvm-svn: 134760

llvm-svn: 134759

llvm-svn: 134758

llvm-svn: 134757

llvm-svn: 134756

llvm-svn: 134755

llvm-svn: 134754

Default 64-bit target features and SSE2 on when a triple specifies x86-64.  Clean up all the other hacks which are now unnecessary.

llvm-svn: 134753

llvm-svn: 134752

According to Intel Application Note 485, this value is used for
"Intel Core i7 and Intel Xeon processor".  Just include it with the other
"corei7-avx" entries.

llvm-svn: 134750

This tightens up checking for overflow in alloca sizes, based on feedback
from Duncan and John about the change in r132926.

llvm-svn: 134749

The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746

you can do things like:

(lldb) target variable g_global.a
(lldb) target variable *g_global.ptr
(lldb) target variable g_global.ptr[1]

llvm-svn: 134745

http://llvm.org/bugs/show_bug.cgi?id=10305

llvm-svn: 134744

llvm-svn: 134743

is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742

llvm-svn: 134741

llvm-svn: 134739

Found by valgrind.

llvm-svn: 134738

No functional change.

llvm-svn: 134737

llvm-svn: 134736

RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

llvm-svn: 134735

llvm-svn: 134734

Found by valgrind.

llvm-svn: 134733

llvm-svn: 134732