llvm-svn: 53680

While this is not a wonderful organizing principle, it
does make it easy to find routines, and clear where to
insert new ones.

llvm-svn: 53672

llvm-svn: 53671

llvm-svn: 53636

just use the AllNodes order, which is at least relatively stable
across runs.

llvm-svn: 53632

llvm-svn: 53613

In LegalizeDAG the value is zero-extended to
the new type before byte swapping.  It doesn't
matter how the extension is done since the new
bits are shifted off anyway after the swap, so
extend by any old rubbish bits.  This results
in the final assembler for the testcase being
one line shorter.

llvm-svn: 53604

llvm-svn: 53603

No change in functionality.

llvm-svn: 53602

llvm-svn: 53590

the BB member to the current basic block after emitting
instructions.

llvm-svn: 53567

don't have value names, so use print instead of getName() to get a
useful string.

llvm-svn: 53563

llvm-svn: 53562

Remove support for this.

llvm-svn: 53559

non-power-of-two vectors.

llvm-svn: 53558

than the vector element type.  Don't forget to
handle this when the insertion index is not a
constant.

llvm-svn: 53556

extending load of a vector.  Handle this case when
splitting vector loads.  I'm not completely sure
what is supposed to happen, but I think it means
hi should be set to undef.  LegalizeDAG does not
consider this case.

llvm-svn: 53555

stores of one-element vectors.  Also, neaten the
handling of INSERT_VECTOR_ELT when the inserted
type is larger than the vector element type.

llvm-svn: 53554

are used for passing huge immediates in inline ASM
from the front-end straight down to the ASM writer.
Of course this is a hack, but it is simple, limited
in scope, works in practice, and is what LegalizeDAG
does.

llvm-svn: 53553

llvm-svn: 53504

Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503

llvm-svn: 53502

instead of using the frame index for the SVOffset, which was
inconsistent.

llvm-svn: 53486

llvm-svn: 53481

llvm-svn: 53480

use a timer group for the timers in SelectionDAGISel. Also,
Split scheduling out from emitting, to give each their own
timer.

llvm-svn: 53476

llvm-svn: 53471

be no need to split the result of a vector RET node,
since they are always already legal.

llvm-svn: 53462

SINT_TO_FP libcall plus additional operations:
it might as well be a direct UINT_TO_FP libcall.
So only turn it into an SINT_TO_FP if the target
has special handling for SINT_TO_FP.

llvm-svn: 53461

llvm-svn: 53460

was presumably added after the rest of the code was
copied to LegalizeTypes.

llvm-svn: 53459

on 16 bit machines.

llvm-svn: 53458

when working on legalizetypes.  Both legalizetypes and legalizeops now
produce hte same code for CodeGen/ARM/fcopysign.ll.

llvm-svn: 53435

llvm-svn: 53434

other passes.

llvm-svn: 53415

llvm-svn: 53414

Lack of these caused a bootstrap failure with Fortran
on x86-64 with LegalizeTypes turned on.  While there,
be nice to 16 bit machines and support expansion of
i32 too.

llvm-svn: 53408

Be nice to 16 bit machines by supporting FP_TO_XINT
expansion for these.

llvm-svn: 53407

llvm-svn: 53406

was doing there: FP_ROUND returns a float, not an
integer.

llvm-svn: 53405