Commits · bf9bba47a17d146bc1433858739c615867096b80 · Roger Ferrer / llvm-epi-0.8

Nov 03, 2011
- build: Add initial cut at LLVMBuild.txt files. · bf9bba47
  Daniel Dunbar authored Nov 03, 2011
```
llvm-svn: 143634
```
  bf9bba47
- Add new X86 AVX2 VBROADCAST instructions. · 0e7cbbab
  Craig Topper authored Nov 03, 2011
```
llvm-svn: 143612
```
  0e7cbbab
- Add support for sign-extending non-legal types in SelectSIToFP(). · bf5f4bec
  Chad Rosier authored Nov 03, 2011
```
llvm-svn: 143603
```
  bf5f4bec
- Fixed parameter name. · 1f4603d4
  Lang Hames authored Nov 02, 2011
```
llvm-svn: 143594
```
  1f4603d4
Nov 02, 2011
- Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. · 9929c423
  Lang Hames authored Nov 02, 2011
```
llvm-svn: 143582
```
  9929c423
- Add support for comparing integer non-legal types. · 9cf803c4
  Chad Rosier authored Nov 02, 2011
```
llvm-svn: 143559
```
  9cf803c4
- Fix the issue that r143552 was trying to address the _right_ way. ... · fbb704f5
  Owen Anderson authored Nov 02, 2011
```
Fix the issue that r143552 was trying to address the _right_ way.  One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear.  This fixes round tripping on this instruction.

llvm-svn: 143557
```
  fbb704f5
- The rules disallowing single-register reglist operands only apply to the POP... · ec5c5f70
  Owen Anderson authored Nov 02, 2011
```
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions.  Revert r143552.

llvm-svn: 143553
```
  ec5c5f70
- Register list operands are not allowed to contain only a single register. ... · fad59dab
  Owen Anderson authored Nov 02, 2011
```
Register list operands are not allowed to contain only a single register.  Alternate encodings are used in that case.

llvm-svn: 143552
```
  fad59dab
- Factor out an EmitIntExt function. No functionality change intended. · 4489f948
  Chad Rosier authored Nov 02, 2011
```
llvm-svn: 143547
```
  4489f948
- More AVX2 instructions and intrinsics. · a47b05c7
  Craig Topper authored Nov 02, 2011
```
llvm-svn: 143536
```
  a47b05c7
- Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. · 682b8506
  Craig Topper authored Nov 02, 2011
```
llvm-svn: 143529
```
  682b8506
- Factor out a SelectTrunc function. No functionality change intended. · ee7e4525
  Chad Rosier authored Nov 02, 2011
```
llvm-svn: 143523
```
  ee7e4525
Nov 01, 2011
- ARM label operands can be quoted. · 5c6b6346
  Jim Grosbach authored Nov 01, 2011
```
For example, labels from Objective-C sources.

llvm-svn: 143511
```
  5c6b6346
- ARM label operands can have an optional '#' before them. · 7f1f3bd8
  Jim Grosbach authored Nov 01, 2011
```
llvm-svn: 143510
```
  7f1f3bd8
- Fix disassembly of some VST1 instructions. · 69e54a74
  Owen Anderson authored Nov 01, 2011
```
llvm-svn: 143507
```
  69e54a74
- rename getHostTriple into getDefaultTargetTriple · 94441fba
  Sebastian Pop authored Nov 01, 2011
```
llvm-svn: 143502
```
  94441fba
- Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant... · 3f5eccbe
  Eli Friedman authored Nov 01, 2011
```
Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value.  Fixes PR11289.

llvm-svn: 143498
```
  3f5eccbe
- Don't fold negative offsets into cp / dp accesses to avoid relocation errors. · 56ce0932
  Richard Osborne authored Nov 01, 2011
```
This can happen if the address + addend is less than the start of the cp / dp.

llvm-svn: 143459
```
  56ce0932
- ARM VLD/VST assembly parsing for symbolic address operands. · fb2f1d61
  Jim Grosbach authored Nov 01, 2011
```
llvm-svn: 143413
```
  fb2f1d61
- Add support for new atomics to cpp backend. Misc other fixes while I'm here. PR11268. · d28ddbff
  Eli Friedman authored Oct 31, 2011
```
llvm-svn: 143406
```
  d28ddbff
Oct 31, 2011
- ARM VST1 w/ writeback assembly parsing and encoding. · 05df4602
  Jim Grosbach authored Oct 31, 2011
```
llvm-svn: 143369
```
  05df4602
- ARM writeback vs. stride operands for VST/VLD. · e4c8e692
  Jim Grosbach authored Oct 31, 2011
```
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.

llvm-svn: 143356
```
  e4c8e692
- More not-crashing NEON disassembly updates for the vld refactoring. · 40703f42
  Owen Anderson authored Oct 31, 2011
```
llvm-svn: 143351
```
  40703f42
- Begin adding AVX2 instructions. No selection support yet other than intrinsics. · cfcfdf2a
  Craig Topper authored Oct 31, 2011
```
llvm-svn: 143331
```
  cfcfdf2a
- Switch new .file directive emission off by default, change llc's flag for it to · aab6169e
  Nick Lewycky authored Oct 31, 2011
```
-enable-dwarf-directory.

llvm-svn: 143326
```
  aab6169e
Oct 30, 2011

Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. · 228d9131
Craig Topper authored Oct 30, 2011
```
llvm-svn: 143319
```
228d9131

X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift... · 7402ee6e

Benjamin Kramer authored Oct 30, 2011

X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.

llvm-svn: 143315

7402ee6e

· c602b2c4

Nadav Rotem authored Oct 30, 2011

Fix pr11266.

On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311

c602b2c4

Oct 29, 2011
- PPC: Disable moves for all CR subregisters. · ff91dd9f
  Benjamin Kramer authored Oct 29, 2011
```
Should fix assertion failures on ppc buildbots.

llvm-svn: 143290
```
  ff91dd9f
- Revert r143206, as there are still some failing tests. · 9b9c9701
  Dan Gohman authored Oct 29, 2011
```
llvm-svn: 143262
```
  9b9c9701
- ARM mode 'mov' to 'mvn' assembler alias. · 3d785ede
  Jim Grosbach authored Oct 28, 2011
```
llvm-svn: 143237
```
  3d785ede
- Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". · b009a872
  Jim Grosbach authored Oct 28, 2011
```
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
```
  b009a872
Oct 28, 2011
- Specify that the high bit of the alignment field is fixed to 0 on these instructions. · 409b694c
  Owen Anderson authored Oct 28, 2011
```
llvm-svn: 143220
```
  409b694c
- Make changes necessary in LowerFormalArguments to support Mips64. · 104b7e3f
  Akira Hatanaka authored Oct 28, 2011
```
llvm-svn: 143218
```
  104b7e3f
- Make changes necessary in LowerCall to support Mips64. · b20a325b
  Akira Hatanaka authored Oct 28, 2011
```
llvm-svn: 143217
```
  b20a325b
- Add variable IsO32 to MipsTargetLowering. · 7989f15d
  Akira Hatanaka authored Oct 28, 2011
```
llvm-svn: 143213
```
  7989f15d
- Reapply r143202, with a manual decoding hook for SWP. This change... · dde461c8
  Owen Anderson authored Oct 28, 2011
```
Reapply r143202, with a manual decoding hook for SWP.  This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.

llvm-svn: 143208
```
  dde461c8
- Reapply r143177 and r143179 (reverting r143188), with scheduler · 73057ad2
  Dan Gohman authored Oct 28, 2011
```
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.

llvm-svn: 143206
```
  73057ad2
- Revert r143202. · effd0944
  Owen Anderson authored Oct 28, 2011
```
llvm-svn: 143203
```
  effd0944