- Sep 20, 2008
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Evan Cheng authored
Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. llvm-svn: 56381
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Evan Cheng authored
llvm-svn: 56378
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Evan Cheng authored
llvm-svn: 56377
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Dan Gohman authored
llvm-svn: 56376
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Evan Cheng authored
llvm-svn: 56372
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Dan Gohman authored
results in better code for globals. Also, unbreak the local CSE for GlobalValue stub loads. llvm-svn: 56371
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- Sep 19, 2008
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Dale Johannesen authored
have previously been assigned conflicting physreg. llvm-svn: 56364
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Evan Cheng authored
llvm-svn: 56352
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Gabor Greif authored
llvm-svn: 56349
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Gabor Greif authored
untested, Use::swap() is definitely not done yet llvm-svn: 56348
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Duncan Sands authored
Unfortunately this means removing one regression test of GlobalsModRef because I couldn't work out how to perform it without MarkModRef. llvm-svn: 56342
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Duncan Sands authored
can get the readnone/readonly attributes, and gives them it. The plan is to remove markmodref (which did the same thing by querying GlobalsModRef) and delete the analogous functionality from GlobalsModRef. llvm-svn: 56341
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Dale Johannesen authored
and redo as linked list walk. Logic moved into RA. Per review feedback. llvm-svn: 56326
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Devang Patel authored
Fixes PR 2805 llvm-svn: 56321
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Dan Gohman authored
catches a fair number of common cases. Note that this currently causes Fast-ISel to leave behind lots of dead instructions. Those will be dealt with in subsequent commits. llvm-svn: 56320
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Bill Wendling authored
Thanks to Ji Young Park for the patch! llvm-svn: 56316
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Devang Patel authored
llvm-svn: 56315
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Evan Cheng authored
llvm-svn: 56314
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- Sep 18, 2008
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Dan Gohman authored
llvm-svn: 56311
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Dan Gohman authored
defs to be necessarily live. llvm-svn: 56310
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Dan Gohman authored
copy of the BURRList scheduler, but with several parts ripped out, such as backtracking, online topological sort maintenance (needed by backtracking), the priority queue, and Sethi-Ullman number computation and maintenance (needed by the priority queue). As a result of all this, it generates somewhat lower quality code, but that's its tradeoff for running about 30% faster than list-burr in -fast mode in many cases. This is somewhat experimental. Moving forward, major pieces of this can be refactored with pieces in common with ScheduleDAGRRList.cpp. llvm-svn: 56307
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Evan Cheng authored
Preliminary support for systems which require changing JIT memory regions privilege from read / write to read / executable. llvm-svn: 56303
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Evan Cheng authored
llvm-svn: 56301
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Evan Cheng authored
llvm-svn: 56300
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Evan Cheng authored
llvm-svn: 56299
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- Sep 17, 2008
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Dan Gohman authored
over having it in a register. And wait until after checking type legality before requesting that the callee address be placed in a register. Also, fix support for calls with void return type. This speeds up fast-isel isel time by about 15% and reduces instruction counts by about 3% overall on certain testcases. It also changes many indirect calls to direct calls. llvm-svn: 56292
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Dale Johannesen authored
with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. llvm-svn: 56290
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Evan Cheng authored
llvm-svn: 56287
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Devang Patel authored
llvm-svn: 56286
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Devang Patel authored
This one slipped through cracks very well. llvm-svn: 56284
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Dan Gohman authored
llvm-svn: 56281
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Evan Cheng authored
llvm-svn: 56277
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Evan Cheng authored
llvm-svn: 56276
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Dan Gohman authored
up some new ascii art to illustrate what it does. This change currently has no effect on generated code. llvm-svn: 56270
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Dan Gohman authored
be used with fast-isel. llvm-svn: 56268
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Bill Wendling authored
function with appropriate parameters. This allows us to support blocks on PPC. llvm-svn: 56267
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Evan Cheng authored
When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. llvm-svn: 56258
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Dan Gohman authored
ConstantPoolSDNode, using the target's preferred alignment for the constant type. In LegalizeDAG, when performing loads from the constant pool, the ConstantPoolSDNode's alignment is used in the calls to getLoad and getExtLoad. This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly choosing the ABI alignment for constant pool loads when Alignment == 0. The incorrect alignment is only a performance issue when ABI alignment does not equal preferred alignment (i.e., on x86 it was generating MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI alignment for 128bit vectors is forced to 1 byte.) Patch by Paul Redmond! llvm-svn: 56253
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- Sep 16, 2008
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Bill Wendling authored
Apologies for the thrashing. llvm-svn: 56251
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Dan Gohman authored
llvm-svn: 56250
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