Commits · c0952c8a08098f7d1f97d468d445cb94b034699f · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Oct 10, 2018
- Revert "[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG." · c0952c8a
  Carlos Alberto Enciso authored Oct 10, 2018
  c0952c8a
- [DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG. · e7a347e5
  Carlos Alberto Enciso authored Oct 10, 2018
  e7a347e5
- [X86] Remove FeatureRTM from Skylake processor list · 02c62aa5
  Craig Topper authored Oct 10, 2018
  02c62aa5
- [PowerPC][NFC] Add a test case for extract and store patterns · ec527dac
  Nemanja Ivanovic authored Oct 10, 2018
  ec527dac
- [AVR] Fix the 'call.ll' CodeGen test · 30ef1d60
  Dylan McKay authored Oct 10, 2018
  30ef1d60
- [PowerPC] Fix the assert of ISD::SIGN_EXTEND_INREG when type is v2i16 and v2i8 · bc158635
  QingShan Zhang authored Oct 10, 2018
  bc158635
- [WebAssembly] Fix fneg lowering · 108e98ec
  Thomas Lively authored Oct 10, 2018
  108e98ec
- [WebAssembly] Handle V128 register class in explicit locals pass · 409f5840
  Thomas Lively authored Oct 09, 2018
  409f5840
- [DAGCombiner] Expand combining of FP logical ops to sign-setting FP ops · 72d4866e
  Nemanja Ivanovic authored Oct 09, 2018
  72d4866e
- [PowerPC][NFC] Commit nabs test case in preparation for committing D44548 · c62dfe51
  Nemanja Ivanovic authored Oct 09, 2018
  c62dfe51
- Recommit r343993: [X86] condition branches folding for three-way conditional codes · 3d2efdfd
  Rong Xu authored Oct 09, 2018
  3d2efdfd
Oct 09, 2018
- [PowerPC] Implement hasBitPreservingFPLogic for types that can be supported · 87873d04
  Nemanja Ivanovic authored Oct 09, 2018
  87873d04
- [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in... · f6d84008
  Craig Topper authored Oct 09, 2018
  f6d84008
- [X86] Autogenerate complete checks. NFC · 4ea56962
  Craig Topper authored Oct 09, 2018
  4ea56962
- [AArch64][x86] add tests for bitcasted fnabs; NFC · a875030a
  Sanjay Patel authored Oct 09, 2018
  a875030a
- [x86] use demanded bits to simplify masked store codegen · f5fac182
  Sanjay Patel authored Oct 09, 2018
  f5fac182
- [SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to SimplifyDemandedBits · 23f88031
  Simon Pilgrim authored Oct 09, 2018
  23f88031
- Fix buildbot failures with the newly added test case (triple was missing). · c8fe772a
  Nemanja Ivanovic authored Oct 09, 2018
  c8fe772a
- [PowerPC] Remove self-copies in pre-emit peephole · 4c0b110e
  Nemanja Ivanovic authored Oct 09, 2018
  4c0b110e
- [X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors · 720db8ed
  Simon Pilgrim authored Oct 09, 2018
  720db8ed
- ExpandPostRAPseudos: Fix alldefsAreDead() not removing operands · 1c96c968
  Matthias Braun authored Oct 09, 2018
  1c96c968
- [MIPS GlobalISel] Legalize i64 add · aa97890d
  Petar Jovanovic authored Oct 08, 2018
  aa97890d
- [X86] Revert r343993 condition branches folding for three-way conditional codes · 47fd0151
  Rong Xu authored Oct 08, 2018
  47fd0151
Oct 08, 2018
- [x86] add tests for phaddd/phaddw; NFC · 6205ba0e
  Sanjay Patel authored Oct 08, 2018
  6205ba0e
- [X86] condition branches folding for three-way conditional codes · 67b1b328
  Rong Xu authored Oct 08, 2018
  67b1b328
- [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions · 823549a6
  Scott Linder authored Oct 08, 2018
  823549a6
- [X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectors · 6fc8d055
  Simon Pilgrim authored Oct 08, 2018
  6fc8d055
- AMDGPU/GlobalISel: Select amdgcn.cvt.pkrtz to 64-bit instructions · 14d8807d
  Tom Stellard authored Oct 08, 2018
  14d8807d
- AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics · ea36cd59
  Nicolai Haehnle authored Oct 08, 2018
  ea36cd59
- [x86] add hadd test with no undefs, remove duplicate tests; NFC · 8459465a
  Sanjay Patel authored Oct 08, 2018
  8459465a
- [x86] simplify hadd tests; NFC · d48789c0
  Sanjay Patel authored Oct 08, 2018
  d48789c0
- [AMDGPU] Add an AMDGPU specific atomic optimizer. · 66416574
  Neil Henning authored Oct 08, 2018
  66416574
- [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled · 367b4741
  Oliver Stannard authored Oct 08, 2018
  367b4741
- [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI · c922116a
  Oliver Stannard authored Oct 08, 2018
  c922116a
- [AArch64][v8.5A] Branch Target Identification code-generation pass · 250e5a5b
  Oliver Stannard authored Oct 08, 2018
  250e5a5b
- [GlobalIsel][X86] Support G_UDIV/G_UREM/G_SREM · 1aedf203
  Alexander Ivchenko authored Oct 08, 2018
  1aedf203
- [x86] add 16 missed hadd patterns (PR39195); NFC · 60badd75
  Sanjay Patel authored Oct 08, 2018
  60badd75
- [ARM] Account for implicit IT when calculating inline asm size · 6f36cd4d
  Peter Smith authored Oct 08, 2018
  6f36cd4d
- [AArch64] Fix verifier error when outlining indirect calls · 9ecdac8e
  Oliver Stannard authored Oct 08, 2018
  9ecdac8e
- [RISCV] Update alu8.ll and alu16.ll test cases · 5af6c149
  Alex Bradbury authored Oct 08, 2018
  5af6c149