lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'

llvm-svn: 115064

llvm-svn: 115061

LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.

llvm-svn: 115047

llvm-svn: 115043

One Printer to lower them all and in the back end bind them.


(Remove option to use the old non-MC asm printer.)

llvm-svn: 115038

added some doxygen on the way

llvm-svn: 115033

llvm-svn: 115029

llvm-svn: 115027

order as cctools for diffability.

llvm-svn: 115022

are defined to emit the 0x67 prefix byte.  rdar://8482675

llvm-svn: 115021

operands.

With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up.  This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'

llvm-svn: 115019

Clean up cvttps2dq by removing some redundant implementations of the
same instruction.  rdar://8456382

llvm-svn: 115018

llvm-svn: 115017

an instruction that requires a WHOLE NEW wonderful kind of alias.

llvm-svn: 115015

MCStreamer to emit into instead of an MCInst to fill in.  This allows the
matcher extra flexibility and is more convenient.

llvm-svn: 115014

problems with phi-nodes in blocks that have hard and not virtual registers.

Accordingly update branch handling to compensate.

llvm-svn: 115013

llvm-svn: 115011

llvm-svn: 115010

llvm-svn: 115009

Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.

llvm-svn: 115008

llvm-svn: 115005

llvm-svn: 115001

llvm-svn: 114999

cost modeling for if-conversion.  Now if only we had a way to estimate the misprediction probability.

Adjsut CodeGen/ARM/ifcvt10.ll.  The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.

llvm-svn: 114995

llvm-svn: 114994

  ARMTargetMachine.cpp:53: error: control reaches end of non-void function

llvm-svn: 114992

Patch by Evzen Muller!

llvm-svn: 114991

Rather than having arbitrary cutoffs, actually try to cost model the conversion.

For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.

llvm-svn: 114973

This should make the arm-linux self-host buildbot happy again.

llvm-svn: 114964

llvm-svn: 114953

llvm-svn: 114952

llvm-svn: 114949

llvm-svn: 114948

llvm-svn: 114947

llvm-svn: 114943

accesses for ARM targets that would otherwise allow it.  Radar 8465431.

llvm-svn: 114941

now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.

llvm-svn: 114934

llvm-svn: 114931

llvm-svn: 114930

enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.

llvm-svn: 114915