llvm-svn: 67874

llvm-svn: 67848

llvm-svn: 67846

improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html), but that code is VERY brittle.

This patch just makes it a bit more resistant.

llvm-svn: 67843

llvm-svn: 67784

llvm-svn: 67765

llvm-svn: 67742

llvm-svn: 67739

llvm-svn: 67738

llvm-svn: 67737

llvm-svn: 67736

  %a = ...
  %b = and i32 %a, 2
  %c = srl i32 %b, 1
  %d = br i32 %c, 

into

  %a = ...
  %b = and %a, 2
  %c = X86ISD::CMP %b, 0
  %d = X86ISD::BRCOND %c ...

This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.

llvm-svn: 67728

llvm-svn: 67727

llvm-svn: 67681

llvm-svn: 67668

llvm-svn: 67667

to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.

llvm-svn: 67588

llvm-svn: 67580

same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.

llvm-svn: 67562

explicitly flush it.

llvm-svn: 67526

llvm-svn: 67518

Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.

llvm-svn: 67512

llvm-svn: 67507

i8 return values.

llvm-svn: 67502

Handle odd registers allocation in FGR32.

llvm-svn: 67422

llvm-svn: 67416

llvm-svn: 67412

llvm-svn: 67373

Removed unncessary code. No functionality change.

llvm-svn: 67371

for those architectures that support the instruction.

llvm-svn: 67363

llvm-svn: 67287

in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.

llvm-svn: 67286

llvm-svn: 67280

not safe in general because the immediate could be an arbitrary
value that does not fit in a 32-bit pcrel displacement.  
Conservatively fall back to loading the value into a register
and calling through it.

We still do the optzn on X86-32.

llvm-svn: 67142

Revert inadvertent mis-fix of fneg.

llvm-svn: 67084

llvm-svn: 67072

llvm-svn: 67071

- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.

llvm-svn: 67067

Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the
llvm-gcc bootstrap a bit further along.

llvm-svn: 67048

This causes incorrect stack frame allocation when the last object is an array allocated on the stack which would lead
the compiled program to run over its stack. Thanks to Gil Dogon

llvm-svn: 67034